Dump verilog array in gtkwave

Question

Is there a way to dump the memory in verilog using vcd dump? Since now i have written this:

module sampler(clk, pixel);
 input clk;
 input[7:0] pixel;
 wire[7:0] pixel;
 reg [7:0] macro_block [0:63];
 reg [5:0] address;
 always @ (posedge clk or negedge clk) begin
 macro_block[address]=pixel;
 address<=address+1;
 end
endmodule
module tb();
 reg clk;
 reg[7:0] pixel;
 sampler s(clk,pixel);
 initial begin
 $dumpfile("test.vcd");
 $dumpvars(0,tb);
 clk=0;
 pixel=1;
 $monitor("%g %b",$time, clk);
 #5 $finish;
 end
 always begin
 #1 clk <= ~clk;
 end
endmodule

but the array macro_block is not shown in gtkwave, is it possible to shown?

Answer 1

Depends on your simulator. For Icarus, I think you need an explicit dumpvars statement for every array row you want to dump. I don't recall if you need the [msb:lsb] subscript. For CVC, you can use the +dump_arrays plusarg. I use CVC all the time and view arrays in gtkwave.