Simulation an interpolation ( adding zeros) in VHDL

Question

Given an input vector :

data_in: in std_logic_vector( 5 downto 0);

I am going to shift the data_in and create an array of data:

for i in 1 to 9 loop
 shift_data_in(i) <= shift_data_in(i - 1); 
end loop;

shift_data_in is an array of vectors:

type data_array is array (integer range 0 to 9) of std_logic_vector ( 5 downto 0); 
signal shift_data_in: data_array := (others => (others => '0')); 

The next step is inserting 0s between original data_in:

if Int_enb= '1' then
 shift_data_in(0) <= data_in;
else -
 shift_data_in(0) <= (others => '0');
end if;

I send shift_data_in as output ( check this implementation):

data_out <= shift_data_in(9);

A test bench file will give me a value for Int_enb:

if(4 = counter) then 
 counter <= 0;
 Int_enb <= '1';
else
 counter <= counter + 1;
 Int_enb <= '0';
end if;

I don't see any syntax error. The code can be compiled, but as output it gives me 0. Could someone help to find Where I have mistaken?

EDIT 1

The main file( design)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
entity main is
GENERIC
 (
 bits: integer := 12; 
 taps: integer := 69 );
 Port
 (
 Clk: in STD_LOGIC; 
 Rst: in std_logic;
 data_in: in std_logic_vector( (bits - 1) downto 0);
 FirEn: in std_logic; 
 Int_enb : in std_logic :='0'; 
 
 data_out: out std_logic_vector( (bits - 1) downto 0)
 );
 end main;
 architecture Behavioral of main is
 type data_array is array (integer range 0 to (taps - 1)) of std_logic_vector ( ( bits-1 ) downto 0); 
 signal shift_data_in : data_array := (others => (others => '0'));
begin
 main_process : process(Clk)
 begin 
 if rising_edge(Clk) then
 if Rst = '1' then 
 data_out <= (others => '0');
 elsif FirEn = '1' then
 for N in 1 to (taps - 1) loop
 shift_data_in(N) <= shift_data_in(N - 1); 
 end loop; 
 if Int_enb = '1' then
 shift_data_in(0) <= data_in;
 else 
 shift_data_in(0) <= (others => '0');
 end if; 
 data_out <= shift_data_in(taps - 1);
 
 end if;
 end if; 
 end process main_process;
 
 
 end Behavioral;

and the test bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use STD.textio.all;
use ieee.std_logic_textio.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity main_tb is
end main_tb;
architecture Behavioral of main_tb is
 constant bits: integer := 12; 
 constant taps: integer := 69; 
 constant M: integer := 4;
 
 signal Clk : std_logic := '0';
 signal Rst : std_logic := '0';
 signal FirEn : std_logic := '1';
 signal Int_enb : std_logic := '0';
 signal data_in : std_logic_vector( (bits - 1) downto 0) := (others => '0');
 signal data_out : std_logic_vector( (bits -1) downto 0);
 constant Clk_period : time := 20 ns; -- Clock period definitions
 signal counter : integer range 0 to M - 1 := 0; 
 COMPONENT main
 PORT(
 Clk: in STD_LOGIC; 
 Rst: in std_logic; 
 data_in: in std_logic_vector( (bits - 1) downto 0);
 FirEn: in std_logic; -- enables multiply add chain
 Int_enb: in std_logic :='1'; -- signals new FIR Input
 
 data_out: out std_logic_vector( (bits - 1) downto 0)
 
 );
 END COMPONENT;
begin
UUT : main PORT MAP(
--uut : entity work.main port map ( 
 Clk => Clk,
 Rst => Rst,
 data_in => data_in,
 FirEn => FirEn,
 Int_enb => Int_enb,
 data_out => data_out
 );
 
 Clk_process :process --
 begin
 Clk <= '0';
 wait for Clk_period/2;
 Clk <= '1';
 wait for Clk_period/2;
 end process;
 
 generate_clk_enable_process : process (Clk)
 begin
 if (rising_edge(Clk)) then
 if((M -1) = counter) then 
 counter <= 0;
 Int_enb <= '1';
 else
 counter <= counter + 1;
 Int_enb <= '0';
 end if; 
 end if; 
 end process generate_clk_enable_process;
 
 
process 
begin 
 Rst <= '1';
 FirEn <= '0';
 wait until rising_edge(clk);
 Rst <= '0';
 FirEn <= '1';
 data_in <= "000101000100";
 wait until rising_edge(clk);
 data_in <= "010101010101";
 wait until rising_edge(clk);
 data_in <= "001001010001";
 wait until rising_edge(clk) ;
 data_in <= "000100110010";
 wait until rising_edge(clk) ;
 data_in <= "000100110010";
 wait until rising_edge(clk);
 data_in <= "001001010001";
 wait until rising_edge(clk) ;
 data_in <= "000000000000";
 wait until rising_edge(clk);
 data_in <= "110110101111";
 wait until rising_edge(clk);
 data_in <= "111011001110";
 wait until rising_edge(clk); 
 data_in <= "111011001110" ;
 wait;
 end process;
end Behavioral;
 
 

EDIT 2

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EDIT 3

Can I use integer- vector as input vector? Does it make sense in a simulation a filter?

[In the test bench I would send a std_logic_vector, but convert first to integer. In the design file I would work with integer type of data. I believe then I don't need think about an extension of vector in addition step, for example.]

• Dave Tweed: Show us the complete module, along with the testbench you use to drive the simulation. Otherwise, there's no way we can guess what your problem might be.
• LenaPark: @DaveTweed I have added
• Dave Tweed: Which part of "did you run the simulator long enough" did you not understand?
• LenaPark: @DaveTweed I got what you have meant. :)
• Dave Tweed: In the Vivado built-in simulator, use the "Run For..." command and give it a value of at least 2 us. In the Wave window, make sure you zoom out far enough to see all of the results.

Answer 1

The reason you're getting zero at the output is that you're only feeding zeros in.

Your sampling logic only accepts a new data_in value every five clock cycles, or every 100 ns. But for some reason, you're feeding data values at 10 ns intervals, and even more oddly, every fifth value is zero. So, your shift register only ever sees zero when it samples the data.

• LenaPark: I have done changes in the test bench...it is still 0 in output
• LenaPark: have i an error in the main file or in the test bench?
• Dave Tweed: The testbench looks the same as before to me. But the error is definitely in the testbench, since it controls both the sampling interval and the data input, and it is doing so inconsistently.
• Dave Tweed: I didn't compute it. At first, I just ran the simulation for a few hundred ns. Then I realized that I didn't remember the length of your delay line, and after I checked, I just increased the run time to 10 us. But the computation would be 20 ns clock period * 69 taps = at least 1380 ns.
• Dave Tweed: Are you hoping to send in the sequence 1, 2, 3, 4, ... and get out 1, 0, 0, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, ... ?