VHDL simulation 'X' output (Vivado)

Question

I'm trying to build a modulo-4 counter using dataflow modeling. I devised the logic circuit like the following;

schematic

^{simulate this circuit – Schematic created using CircuitLab}

I wanted to implement this circuit with VHDL. I started from building an SR-latch. Then, a D-latch, then, a DFF. Finally I used the DFFs to build the circuit.

Following is my VHDL code for the counter,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod4_counter is
 Port (CLK : in std_logic; COUT : out std_logic);
end mod4_counter;
architecture Behavioral of mod4_counter is
component d_flipflop is
 Port (DFF,CLK : in std_logic; QFF,QFFNOT : out std_logic );
end component;
signal dff1d, dff1q, dff1qnot, dff2d, dff2q, dff2qnot : std_logic;
begin
DFF1 : d_flipflop port map(DFF=>dff1d, CLK=>CLK, QFF=>dff1q, 
QFFNOT=>dff1qnot);
DFF2 : d_flipflop port map(DFF=>dff2d, CLK=>CLK, QFF=>dff2q, QFFNOT=>dff2qnot);
dff1d <= dff1q xor dff2q;
dff2d <= dff2qnot;
COUT <= dff1q and dff2q;
end Behavioral;

And the testbench code,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity counter_sim is
end counter_sim;
architecture Behavioral of counter_sim is
component mod4_counter is
 Port (CLK : in std_logic; COUT : out std_logic );
end component;
signal CLK : std_logic;
signal COUT : std_logic;
begin
uut : mod4_counter port map(CLK=>CLK, COUT=>COUT);
clkpr : process
begin
CLK <= '1';
wait for 75ns;
CLK <= '0';
wait for 75ns;
end process;
end Behavioral;

All the underlying components (SR, D latch, DFF) were simulated successfully. But when I simulate this design, COUT is always 'X'. What is wrong here?

• Oldfart: 1/ The actual core of your code is the d_flipflop the code for which is missing. 2/ You probably do not give the register an initial value. 3/ This problem/question appears about once or twice a month. Did you search for previous questions/answers?
• zeke: @Oldfart Yes, I did a search about this issue on the internet. I was suspecting this might be an initial value problem. However, even if I assign a default value to ''COUT'', it still doesn't work. The d_flipflop code is not shared here because it functioned correctly during its simulation, so I assumed it was not the issue here.
• Mitu Raj: Dude, you are missing reset thats why..Also adding init value to COUT does nothing cz it is driven by another net

Answer 1

If you are only trying to implement your circuit then to me it seems that you are over thinking this: first let’s give NAME to the different signals:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Now, let’s right the equations that rules the circuit:

s_3 = s_1 XOR s_2

s_4 = NOT s_2

s_out = s_1 AND s_2

Now, let's write the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 
entity counter_whatever is
 Port(
 i_clock : in std_logic;
 i_reset : in std_logic;
 o_result : out std_logic
 );
end entity;
architecture Behavioural of counter_whatever is
 signal s_1, s_2 : std_logic;
begin
 --the output is not synchronous according to your schematic
 o_result <= s_1 AND s_2;
 --Process that deal with the upper register 
 uper_register : process(i_clock, i_reset)
 variable v_3 : std_logic; 
 begin
 if rising_edge(i_clock) then
 --if a reset occurs
 if i_reset = '1' then
 v_3 := '0';
 s_1 <= '0';
 
 --if no reset occurs
 else
 v_3 := s_1 XOR s_2;
 s_1 <= v_3;
 
 end if;
 end if;
 end process;
 --Process that deal with the lower register 
 lower_register : process(i_clock, i_reset)
 variable v_4 : std_logic; 
 begin
 if rising_edge(i_clock) then
 --if a reset occurs
 if i_reset = '1' then
 v_4 := '0';
 s_2 <= '0';
 
 --if no reset occurs
 else
 v_4 := NOT s_2;
 s_2 <= v_4;
 
 end if;
 end if;
 end process;
 
end architecture;

You can remove the variables, I have added them for more clarity. You can also merge the 2 processes into a single one.

You should have a reset in your process.

I do not understand why you are talking about SR-latch, D-latch or DFF. In your schematic there is juste register (Flip-Flop).

Hope it helps you