In verilog is legal to implement a reset using assign?

Question

I am trying to add a reset to a counter and I have this code, that syntethize perfectly:

module syncRX(clk, signal, detect);
 input clk, signal;
 output [7:0] detect;
 
 reg [7:0] detect_aux = 8'b0;
 reg rst;
 assign detect = detect_aux & ~rst;
 
 freq_div div(.clk(clk), .clk_1khz(clk_1khz));
 
 always @(posedge signal)
 rst <= 1;
 
 always @(posedge clk_1khz)
 detect_aux <= detect_aux + 1;
 
endmodule // top
module freq_div(input clk, output reg clk_1khz);
 reg [12:0] count = 0;
 always @(posedge clk)
 begin
 if(count == 6000)
 begin
 clk_1khz <= ~clk_1khz;
 count <= 0;
 end
 else
 count <= count + 1;
 end
endmodule

The problem is that

 reg rst;
 assign detect = detect_aux & ~rst;

Seams do nothingh. Is legal that I am trying? Thanks

• Dave Tweed: It does nothing because rst is always 0.
• Dave Tweed: Also, given the way you're driving it, rst should be a reg, not a wire.
• Carlos J.: Ups! Thanks Dave, you are right, I just fixed!

Answer 1

as already stated, you never change the value from rst to '1'

next, your rst is no reset in terms of chipdesign, but a clear signal, so rename it to clr.

"all" about real resets for modules: http://www.asic-world.com/tidbits/all_reset.html

Answer 2

As pointed out in comments, in your code rst is always 0, therefore it will never affect the value of detect. If you want the reset to happen, you should make rst an input to your module, and then set it high at some point in your test bench.

But you should also notice that this isn't really a reset behavior. Setting rst high will force the detect output of the module to go to zero, but as soon as rst goes low again detect will return to its previous value as stored in detect_aux. If this were a proper reset, we'd expect the counting to start anew from 0 after rst is released.