\$\begingroup\$
\$\endgroup\$
I declared alu_result
as a reg because I need it to be a variable data type for my case statement. But when i do this, I cannot pass it my write_data
in my datapath_tb module. Is there some work around where I can get this to work?
module alu(input [31:0] input1, input2, input [2:0] control);
parameter SIZE=32;
reg [31:0] alu_result;
reg overflow;
always @(*)
begin
case(control)
0: alu_result = input1 & input2;
1: alu_result = input1 | input2;
2: alu_result = input1 + input2;
3: alu_result = (input1 < input2)?1'b1:1'b0; //unsigned, no additional bits to worry about
4: alu_result = input1 ^ input2;
5: alu_result = ~(input1 | input2);
6: alu_result = input1 - input2;
7: alu_result = (~(input1 + 1) < input2)?1'b1:1'b0; //2's comp is ~ & +1
default: alu_result = input1 & input2;
endcase
if(alu_result > 32'hFFFFFFFF)
begin
overflow <= alu_result;
end
end
endmodule // alu
module datapath_tb();
parameter SIZE = 32;
reg clk;
reg write;
reg [4:0] write_addr;
reg [31:0] write_data;
reg [4:0] read_addr1;
reg [4:0] read_addr2;
wire [31:0] read_data1;
wire [31:0] read_data2;
// Instantiate the register file
Register rf_1 (.clk(clk), .write_en(write), .write_addr(write_addr), .write_data(write_data), .read_addr1(read_addr1), .read_addr2(read_addr2), .read_data1(read_data1), .read_data2(read_data2));
// Instantiate the ALU
alu #(SIZE) alu_1 (.input1(read_data1), .input2(read_data2), .alu_result(write_data)); //Line in question
// Create a clocking signal
always begin
# 10;
clk = 1;
# 10;
clk = 0;
end
initial begin
// Write DIGIT0 into register 0
// Write DIGIT1 into register 1
end
endmodule
asked Aug 5, 2020 at 6:24
1 Answer 1
\$\begingroup\$
\$\endgroup\$
1
Declare your module ports as:
module alu #(parameter SIZE=32) (input wire [SIZE-1:0] input1, input2,
wire [2:0] control,
output reg [SIZE-1:0] alu_result,
reg overflow );
answered Aug 5, 2020 at 7:29
-
\$\begingroup\$ That actually worked. Though I moved out
control
andoverflow
to declare locally. Now I'm just working on connecting it correctly on my datapath_tb module. "alu_result Must be connected to a structural or net expression" Thanks for your help. \$\endgroup\$TheBigBoyOverThere– TheBigBoyOverThere2020年08月05日 16:23:45 +00:00Commented Aug 5, 2020 at 16:23
Explore related questions
See similar questions with these tags.
lang-vhdl