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I have a testbench in SystemVerilog (mostly Verilog, but I'm trying to use more SV) ,and a DUT in just VHDL.

My DUT uses one generic for device selection, but it's not important for testbench sim purposes.

I do not want to modify the DUT. But, I want to save some lines of space in my tb.

Current Code:

interface clk_if
 wire clk;
 modport dut_mp (input clk);
endinterface
module tb;
 clk_if clk_if();
 ....
 dut(
 i_clk_h (clk_if.clk), 
 ....
 );
endmodule

How can I use the modport instead if I do not want to create an extra parameter? Also, can I use different signal names? (clk in interface, i_clk_h in dut)

To add what I'm thinking I would like done:

interface clk_if
 wire clk;
 modport dut_mp (input .i_clk_h(clk)); // I am assuming I could tell interface that the dut has a different signal name but it will be mapped to clk
endinterface
module tb;
 clk_if clk_if();
 ....
 dut(
 clk_if.dut_mp, // clk doesn't have multiple signals but
 rst_if.dut_mp,
 cde_if.dut_mp // this interface would have three signals and I'd like to only call the modport where I assume I could map it in the interface and not here
 ....
 );
endmodule
toolic
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asked Jun 16, 2020 at 19:06
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1 Answer 1

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A modport has no purpose in your case. They are only used to restrict access when an interface appears in a port list declaration. Here you are using an interface the same as another module.

The port signal names never need to match. You have a choice in connecting ports by their position in the port list, or by name .i_clk_h(clk_if.clk), as you have done here.

I'm not sure what you meant by I do not want to create an extra parameter. What extra parameter do you think you are creating?

answered Jun 16, 2020 at 21:02
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  • \$\begingroup\$ most tutorials show that dut(clk_if.dut) would be made. I can call out the signal name to map directly to the interface ports, but I think I can take advantage of modport, especially when I have multiple signals for a particular group. I'd like to replace multiple signal mappping on my top testbench with only several modports in my dut. \$\endgroup\$ Commented Jun 16, 2020 at 21:38
  • \$\begingroup\$ If you can't modify the DUT, there's nothing you can do to take advantage of an interface or its associated modport. \$\endgroup\$ Commented Jun 16, 2020 at 21:42
  • \$\begingroup\$ also, added the ideal code I am looking to implement. I'm assuming either my syntax is wrong or this is not possible at all. \$\endgroup\$ Commented Jun 16, 2020 at 21:42
  • \$\begingroup\$ dang... thats unfortunate. \$\endgroup\$ Commented Jun 16, 2020 at 21:43

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