Verilog Implementation error DFFs and Gates

Question

I am a beginner in verilog and came across this question-

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit. enter image description here

My Code is -

module top_module (
input clk,
input x,
output z
); 
reg q,q1,q2;
always @(posedge clk)
 begin
 q<= q^x;
 q1<= ~q1 && x;
 q2<= ~q2 || x;
 z=~(q | q1 | q2);
 end 
 endmodule

Suggest me where i am going wrong!

• awjlogan: Welcome! You haven't said what's failed, but try moving z=... outside the always block and change it to assign z = ~(q | q1 | q2);
• Akshat Gupta: It previously showed 43 mismatches but now its working fine. Could you please tell me the reason behind this?
• awjlogan: Briefly, you were mixing combinatorial (continuous) assignment (z=...) and sequential logic (q<=...) in an edge sensitive always block. Continous assignments are either done using assign, or in an always @* (Verilog) or always_comb (SystemVerilog) construct.

Answer 1

From the diagram, z is driven by a combinational logic. In the code, you are trying to drive z using sequential logic inside clockedge. You have to either use z as a wire and drive it using assign statement. Or use z as a reg and drive it inside always@* block.

General coding guideline is to not mix blocking and non-blocking assignments in the same always block.