How to implement a flip-flop with synchronous and asyncronous reset?

Question

The flip-flop of FPGA (at least those from Xilinx or the ECP5 family from Lattice) support both synchronous and asynchronous reset (extract from the ECP5 datasheet : "There is control logic to perform set/reset functions (programmable as synchronous / asynchronous)".

The only way I can think of is to have a sync DFF and an async one, and a mux for selecting the data from one or the other:

module DFF(output q, input d, clk, rst, is_rst_sync);
 reg q_from_async_dff;
 always @(posedge clk, posedge rst)
 if (rst)
 q_from_async_dff <= 1'b0;
 else
 q_from_async_dff <= d;
 reg q_from_sync_dff;
 always @(posedge clk)
 if (rst)
 q_from_sync_dff <= 1'b0;
 else
 q_from_sync_dff <= d;
 assign q <= is_rst_sync ? q_from_sync_dff : q_from_async_dff;
endmodule

But it seems unlikely to me that this is the solution used because of the surface waste.

How this kind of sorcery can be implemented efficiently in verilog?

Answer 1

The simple answer is that Xilinx, to use your example, did not implement their flip-flops in Verilog. Their flip-flops are full-custom VLSI designs where the logic cells are highly optimized.

However, we can get a notion of how Xilinx would accomplish this. If there is only one reset input signal for the cell, and we know that the actual implementation of synchronous and asynchronous resets is quite different, then it must be the case that this reset input can be used as either an asynchronous or a synchronous reset but not both.

So, inside Xilinx's actual logic cell they have probably implemented the logic for both asynchronous and synchronous reset. There are two internal signals for possible reset functions. A configuration bit is used to choose which of these signals is actually active and which is disabled.

Answer 2

I don't know why anybody would want this as the asynchronous reset would make the synchronous reset superfluous.

It makes more sense to do this, but with two different reset signals, an asynchronous and a synchronous reset :

 always @(posedge clk, posedge async_reset)
 if (async_reset)
 q <= 1'b0;
 else // this is the clocked section
 if (sync_reset)
 q <= 1'b0;
 else
 q <= d; 

• killruana: I know that anybody with some common sense would not use my solution ^^. Although interesting, your solution does not exactly answer my question because Xilinx uses a single reset signal for synchronous and asynchronous.

Answer 3

Both synchronous or asynchronous resets in design are necessary for different reasons. It has been a religious issue for decades. How to implement a Reset Tree, then test all initial vectors and measure system response and latency is a matter of speed and system DFT philosophy. (design for testability)

Thus specifications are needed before any implementation may be considered. There are volumes of papers written on this subject.

The synchronous reset is just another data input, not a special flop, but it can save Gates for each FF that requires a Reset. The reset logic can easily be synthesized outside the flop itself but may need a pulse stretcher and a guaranteed clock otherwise a "hard" POR.