System verilog: check if logic signal changes at posedge

Question

I'm relatively new to SV. I'm building a testbench in which I want to monitor a signal and take some action if it value changes @ clock posedge. I’m looking for a compact way to this (I.e. not using a register).

logic [31:0] var_signal
Inizialmente
begin
 for(i=0; i<max_cles; i++) begin
 @(posedge clk_i);
 //check if var_signal changed and do something
 end
end

I searched the web and found threads on assertions but it is not what I want to do here. Any hints?

Answer 1

I want to monitor a signal and take some action if it value changes @ clock posedge.

I know you don't want to use a register but it can be test-bench register. You have to make a copy at the clock edge and compare it against the old value:

logic [31:0] new_var_signal
always @(posedge clk_i)
 new_var_signal <= var_signal;
assign signal_changed_at_clock_edge = (new_var_signal != var_signal) ? 1 : 0;

There is a caveat: if the signal can also become 'z' or 'x' you should use:

assign signal_changed_at_clock_edge = (new_var_signal !== var_signal) ? 1 : 0;

Note that you are in an ideal simulation environment and there is no such moment as @(posedge.. That moment is infinitely short.

In a real digital design the signal has to be stable around the clock edge. The time before the clock edge is called the setup time and the time after is called the hold time.

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