VHDL using 'if' to compare a 'variable'

Question

Using Xilinx, I need to compare a 'variable' called 'row', defined as:

variable row : std_logic_vector(2 * n - 1 downto 0);

This line was given to me, now I need an if statement that will execute if row is = 1.

I have tried:

if (row = "1") then

but the IDE warns me that this condition will always result in false? which should not happen.

If I try if (row = '1') then or if (row = 1) then then I get the error:

found '0' definitions of operator "="

Googling this, the only suggestion is to include libraries that I have already included:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

• DonFusili: You need to show more code. If you put the things you have shown so far after each other, your variable should be initalized to (others => 'U') (might depend on simulator), which is not equal to "1". But you might think you initialize it, or you wouldn't ask this question. So supply us with a minimal failing example.
• TonyM: It's telling you the result will always be false because the comparison strings (arguments of "=") are of unequal length. 'row' is a multiple of 2 bits long, "1" is 1 bit long. What is 'n' in this case and will it change? Next, is this variable declared inside a process and should you be using a signal instead? Don't try to carry programming language views into a descriptor language, you'll make a right mess.
• Mitu Raj: That 'n' bugs me. Is that a signal or constant or parameter?

Answer 1

Your variable is a std_logic_vector and you compare it to an integer. You have to cast the std_logic_vector like this:

if(to_integer(signed(row)) = 1) or if(to_integer(unsigned(row)) = 1)

• DonFusili: "1" isn't an integer, it's a std_logic_vector of length 1.
• Kevin Kruse: For completeness, 1 is an integer and '1' is a bit or character.
• Mitu Raj: @Kevin We would like to call it 'bit' because 'character' is a convention in C or C++ which represents a byte.
• Kevin Kruse: @MituRaj "character" is well-defined in VHDL and is valid here. The literal '1' is not necessarily a bit nor a character, it may be either depending on what the literal is compared with or assigned to.
• Mitu Raj: That was just a convention introduced in VHDL for people from software field. We hardware engineers rarely use it in HDL. It makes more sense to assign a bit vector = 01000001 rather than assigning it as a char by 'A'