I have the following example from an answer on a previous post on Stackexchange Electrical Engineering:
show_out <= show when player = '0' else '0';
set_out <= set when player = '0' else '0';
input_out <= input when player = '0' else "00000000";
-- etc.
show_out2 <= show when player = '1' else '0';
set_out2 <= set when player = '1' else '0';
input_out2 <= input when player = '1' else "00000000";
-- etc.
I want to insert it in a process like the one below:
architecture Behavioral of twoplayermux1 is
begin
process (show,set,input,try,player)
begin
-- INSERT THE LINES OF WHEN ELSE ASSIGNMENTS HERE...
end process twoplayermux1;
end Behavioral;
How does the syntax looks like for that?
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\$\begingroup\$ Just replace it with set of if ...else.. endif. (Why do you insists on using a process?) \$\endgroup\$Oldfart– Oldfart2019年11月23日 20:39:26 +00:00Commented Nov 23, 2019 at 20:39
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\$\begingroup\$ I saw your previous post. I think what you are having a problem with is that you are assigning different outputs in each case. So you need to assign both show_out and show_out2 in all your separate cases. The way you have written it, the synthesizer will set show_out = show and show_out2 = show permanently. \$\endgroup\$user110971– user1109712019年11月23日 21:06:02 +00:00Commented Nov 23, 2019 at 21:06
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\$\begingroup\$ @user110971 What about two different if statements in-between "begin" and "end process twoplayermux1"? \$\endgroup\$user164324– user1643242019年11月23日 21:53:46 +00:00Commented Nov 23, 2019 at 21:53
1 Answer 1
The syntax is the same whether inside or outside a process using VHDL-2008. The example slide below shows the syntax. Source for image is: enter link description here. As mentioned in the comment on your question, there's no real need for the process.
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\$\begingroup\$ There's also the
case
-statement \$\endgroup\$JHBonarius– JHBonarius2019年11月26日 21:25:40 +00:00Commented Nov 26, 2019 at 21:25 -
1\$\begingroup\$ Note that some synthesis tools (including Vivado) don't support
when
statements in processes. \$\endgroup\$Caleb Reister– Caleb Reister2019年11月27日 03:37:24 +00:00Commented Nov 27, 2019 at 3:37 -
\$\begingroup\$ @CalebReister have you tried specifying VHDL 2008 type in Vivado? I have certainly synthesized this syntax in Vivado. Perhaps it also depends on your Vivado version. It works in Vivado 2018.3. \$\endgroup\$user_007– user_0072019年11月27日 18:35:01 +00:00Commented Nov 27, 2019 at 18:35
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\$\begingroup\$ @user_007 Yes I did, but I would have been using Vivado 2017.4 when I last tried it. \$\endgroup\$Caleb Reister– Caleb Reister2019年11月27日 19:13:22 +00:00Commented Nov 27, 2019 at 19:13