Verilog Case Statement evaluating all combinations of a 10-bit ADC sample

Question

I have a (hopefully) pretty easy question on case statements. If I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a result value for the output register based on every one of the 1024 cases? Would this eat up LUTs in the FPGA fabric? I considered just doing a large if-else chain, but I've already done it with the large case block and it synthesizes and runs just fine on the Spartan-6 FPGA after doing it for 2 inputs. But now that my design has gotten bigger and I've done that now for 4 different inputs, now the fpga only works when I flash the fpga, but if I power cycle it it boots up to some weird unknown state.

• The Photon: Can you share your actual code? Without it we're only going to be able to answer in very broad generalities that might not actually apply to your use case. Also, have you looked at the synthesis report to see how many LUTs your design actually uses?

Answer 1

I am sampling an incoming signal, which is returned as a 10-bit value, can I evaluate that sample in a case statement and assign a result value for the output register based on every one of the 1024 cases? Would this eat up LUTs in the FPGA fabric?

Yes, the syntax of Verilog allows this.

Would this eat up LUTs in the FPGA fabric?

It depends entirely on the actual truth table you're implementing and how many bits the output value is. The synthesis tool will optimize its output as much as it can. It's possible it could be optimized down to 2 or 3 LUTs per bit of output. Or it could be 10's of LUts per bit of output.

You can check the synthesis report and see exactly how many LUTs your design consumes.

But now that my design has gotten bigger and I've done that now for 4 different inputs, now the fpga only works when I flash the fpga, but if I power cycle it it boots up to some weird unknown state.

This shouldn't have to do with the actual design you implement but just with whether you've correctly flashed the NVM that the FPGA loads from on power cycling.

If you're using a compressed bitstream (I don't recall if Spartan 6 supports this) then it's possible that a small design fits in your NVM, but a complex design does not. You can check the report from the bitstream generator to make sure the size of the bitstream is not bigger than your NVM supports.

• us3rnotfound: The compressed bitstream clue sounds most plausible I am using a Mojo V3 dev board and using MOjo Loader and am downloading a .bin file to the MOjo Spartan 6. I’ll have to investigate the mojo loader and see how it flashes the NVM (is that non volatile memory?).
• The Photon: It's nothing to do with the leader. Check if your two bit files are the same size.
• The Photon: @us3rnotfound, are you using the exact same .bit file for both direct loading and storing in flash? Because IIRC you can't do that. You need slightly different options during bitfile generation depending how the bitfile will be loaded. Will update if I remember exactly what the difference is.
• us3rnotfound: In ISE, for generating a programming file I have specified the generation of a "*.bin" file output as that is what the Mojo Loader needs. ISE still generates the .bit file but I'm not using it. Should I be checking anything else?