error defining multiple parameters

Question

I want to define 19, 16-bit parameter in a way that I can call them like b[0], b[1], b[2], ... this is my code:

 module optimizedSourceFIRfilter(aclk, s_axis_data_tvalid, s_axis_data_tdata, 
 s_axis_data_tready, m_axis_data_tvalid, m_axis_data_tdata);
 input aclk, s_axis_data_tvalid;
 input [15:0] s_axis_data_tdata;
 output s_axis_data_tready, m_axis_data_tvalid;
 output [15:0] m_axis_data_tdata;
 parameter signed [15:0] b [18:0];
 b[0] = 26;
 b[1] = 270;
 b[2] = 963;
 b[3] = 2424;
 b[4] = 4869;
 b[5] = 8259;
 b[6] = 12194;
 b[7] = 15948;
 b[8] = 18666;
 b[9] = 19660;
 b[10] = 18666;
 b[11] = 15948;
 b[12] = 12194;
 b[13] = 8259;
 b[14] = 4869;
 b[15] = 2424;
 b[16] = 963;
 b[17] = 270;
 b[18] = 26;
 end module

however, this is not working and I got these errors:

near "[": syntax error, unexpected '['.

and this one

vlog-13205) Syntax error found in the scope following 'b'. Is there a missing '::'?

how can I solve that??

EDIT: I also changed parameter to reg, but I got the same error messages

Answer 1

You can only initialize an unpacked array parameter in SystemVerilog.

parameter signed [15:0] b [0:18] = {26,270, ... ,26};

In Verilog, you would have to pack the array and the select a slice of the parameter. But each slice would be unsigned.

 parameter [0:(16*19)-1] b = {16'd26, 16'd270, ... , 16'd26};

Then each slice b[I] unpacked would be b[I*16+:16] packed.