SystemVerilog Enumerated Multi-Domain Array -> how to declare/define?

Question

Here is an example how to define the 2*N array of enum types of {S0,S1,S2,S3}:

typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} state_t; (*)

So, each element of the above 2*N array could be either S0 or S1 or S2 or S3.

Let's say the {S0,S1,S2,S3} are defined as a separate enum type:

typedef enum {S0,S1,S2,S3} st_t;

So how now could I rewrite the first statement (*)?

Could it be re-written as the following:

typedef enum st_t [N-1:0][1:0] state_t;

Thank you!

Answer 1

To the best of my knowledge typedef enum logic [N-1:0][1:0]{S0,S1,S2,S3} state_t; should not compile, and I was not able to get it to compile on any simulator on EDAplayground. Enums need a simple vector datatype. logic [N-1:0][1:0] is a double packed array and thereby isn't simple.

If you do not specify the data type of an enum, it is assumed to be an int.

typedef enum st_t [N-1:0][1:0] state_t; has a similar problem as your original statement, but now you define an enum as an double packed enums. Plus you never define the enum values.

What will work:

typedef enum logic [1:0] {S0,S1,S2,S3} st_t;
typedef st_t [N-1:0] state_t;

Or as an unpacked array:

typedef enum logic [1:0] {S0,S1,S2,S3} st_t;
typedef st_t state_t [N];

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Read more about user-defined types (typedef) and enumerations (enum) in IEEE Std 1800-2012 § 6.18 User-defined types and § 6.19 Enumerations

Try differnet combinations on your SystemVerilog simulator or a one of the many simulators on EDA Playground (Use one of the commercial simulators, the free ones have limit if any SV featurs)

• John: Cannot I define the {S0,S1,S2,S3} as a separate type? Something like that: typedef enum {S0,S1,S2,S3} ss_t; typedef enum logic [1:0][ss_t] st_t; typedef st_t state_t [N];
• Greg: You cannot define an enum with another enum. An enum’s datatype must be a simple vector type (ex int, logic [7:0], byte, bit [23:0], etc). If a datatype is not specified then int is assumed. typedef cannot be treated as macros.
• John: Could the above be re-written as following (using `define for substitution): (tick)define ss_t {S0,S1,S2,S3}; typedef enum logic [1:0] (tick)ss_t st_t; typedef st_t state_t [N]; As far as I understand, this is a 3-D array, correct?
• Greg: No, it is a 2-D array. {S0,S1,S2,S3} is the legal content of the enum, it does not determine the bit-width. The logic [1:0] specifies the bit-width, bit-state type (eg: bit vs logic), and if it signed/unsigned. enum logic [1:0] {S0,S1,S2,S3} is an 2-bit unsigned enum where S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11. In contrast enum {S0,S1,S2,S3} is a 32-bit signed enum where S0=32'd0, S1=32'd1, S2=32'd2, S3=32'd3 (there is zero padding)
• John: Greg, thanks a lot for your explanations. Anyway, could the above code be re-written as following: (using `define for substitution): (tick)define ss_t {S0,S1,S2,S3}; typedef enum logic [1:0] (tick)ss_t st_t; typedef st_t state_t [N]; ?