109 bit tree comparator with generate and for loop

Question

I am trying to write Verilog code for a 109-bit tree comparator, but I am still new to the generate loop.

Here is the block diagram for the 109-bit tree comparator.

I have written some code so far but I am not sure if this will work or if I can use 2-d arrays for g and l signals?

parameter NUM_OF_BITS = 220;
parameter NUM_OF_LEVELS = 7;
genvar i,x;
wire [NUM_OF_LEVELS:0][NUM_OF_BITS:0] g, l;
assign g[0] = in0;
assign l[0] = in1;
generate for (x=1; x<NUM_OF_LEVELS; x=x+1) begin: Ls
 for (i=0; i<NUM_OF_BITS/(2**x); i=i+1) begin: MCs
 mag_comp2_1 mc (g[x-1][2*i+1:2*i],l[x-1][2*i+1:2*i],g[x][i],l[x][i]);
 end
end
endgenerate
assign gt = g[7][0];
assign lt = l[7][0]; 

• Ashutosh Jain: I am getting errors that g is not a memory & l is not a memory

Answer 1

The errors you are getting (g is not a memory) should point you to the issue which is that g is not correctly defined as a 2D array.

You declared your 2D arrays as:

wire [NUMBER_OF_ELEMENT-1:0][ELEMENT_WIDTH-1:0] name ;

Which is incorrect.

In Verilog, arrays are declared as:

wire [ELEMENT_WIDTH-1:0] name [NUMBER_OF_ELEMENT-1:0];

You declare the width of any element in a 2D array, then the name of the array, then the number of elements in the array after the name.