Passing and overwriting parameters to Verilog modules

Question

I'm studying the way of passing parameters from one module to another and I have one question.

I have this instance in the top level module.

parameter a= 100;
parameter b = 200 ;
test#(b/(a*2)) test(
 .clk(clk), 
 .reset(reset), 
 .out(out)
 ); 

In test module, I have this header:

module test#(parameter max = 33 )(
 input clk,
 input reset,
 output out
);

So, my question is:

Which value will the module take as input parameter? 33 or 1 ? I mean, Is max=33 overwritten by the one I'm passing from the top level module?

Answer 1

Yes, the value will be overwritten by the one passed from the top module. The value 33 will only be used when there is nothing passed. You can think of it as a default value.

• dave_59: FYI, In SystemVerilog, you can remove default = 33, and you are then required to provide an override in the instance.