Verilog code task inputs do not match the passed values

Question

I am using a task in my module in Verilog, and I have a problem in passing the argument values. The variables defined in the task block as input are not receiving the values that are passed to them while calling this task.

Here is the code:

module carry_addr(Cin,A,B,Sum, Cout,rst_n );
parameter width=3;
parameter bits=1;
input [width:0] A,B;
input Cin,rst_n;
output reg [width:0] Sum;
output reg Cout;
integer k;
reg [width+1:0]C2;
 
task fulladder;
input A1;
input B1;
input C4;
output reg Sum1;
output reg C0;
begin
 Sum1=0;
 C0=0;
 {C0,Sum1}=A1+B1+C4;
end 
endtask
task automatic ripple;
input [bits:0] A2;
input [bits:0] B2;
input C1;
output reg [bits:0]sum2;
output reg cout;
reg [bits:0]sum3,sum4;
reg [bits+1:0] C,C3;
begin
 sum2=0;
 sum3=0;
 sum4=0;
 cout=0;
 C=0;
 C3=0;
 
 C[0]=0; 
 C3[0]=1;
 for (k=0;k<=bits;k=k+1)
 begin 
 fulladder(A2[k],B2[k],C[k],sum3[k],C[k+1]);
 fulladder(A2[k],B2[k],C3[k],sum4[k],C3[k+1]);
 end
 if(C1==0)
 begin
 cout=C[bits+1];
 sum2=sum3;
 end
 else if(C1==1)
 begin
 cout=C3[bits+1];
 sum2=sum4;
 end
end
endtask
always@(rst_n or A or B or Cin)
begin
 if(!rst_n)
 begin
 Sum=0;
 Cout=0;
 C2=0;
 end
 
 C2[0]=Cin;
 for (k=0;k<=width;k=k+bits+1)
 begin
 ripple(A[k+:bits],B[k+:bits],C2[k],Sum[k+:bits],C2[k+bits+1]);
 end
 Cout=C2[width+1];
end
endmodule

In this specifically, A and B values are not copying in the A2 and B2 variables in the ripple task.

Answer 1

The problem with your code is that you have a bit width mismatch between the ripple task input signal and the value you pass to the task.

You declared the A2 input as a 2-bit signal, but you pass it a 1-bit signal. You can prove this to yourself by using $bit to display the bit width of each signal.

Add this line inside the begin block in the task:

$display($size(A2));

Then add this line inside the begin block right before you call the ripple task:

$display($size(A[k+:bits]));

$size(A2) shows 2.

$size(A[k+:bits]) shows 1.

For example, when k=0, A[k+:bits] resolves to A[0 +: 1] which is the same as A[0:0] or A[0]. That is a 1-bit value.

There is another problem, too. I created a simple testbench to drive some values into the design. For some reason, the for loop inside the always block only executes once. It should execute twice (k = 0 and 2). It is not worth debugging this code because you really need a whole new approach. You should re-write the code without using tasks. It is far more common to use Verilog tasks in testbench code than it is in design code.

Answer 2

The issue could be stemming from the fact that you don't have any delays in the verilog code under the for loop (including the code included in the tasks). There could be multiple driver issue.

You can try adding #1 in your for loop and see if that helps.

I notice that the question is pretty old. Might be useful for future exchangers.

• toolic: Adding delays will not solve the problem. It is uncommon for design code to use # delays.