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For a 4-bit signed full adder, the output range in decimal is -8 to +7. I created a 4-bit signed full adder in verilog and simulated it. When I added +5 and +3, I got a sum of -8 and overflow=1. This should be correct right? When I added +3 and -1, I got a sum of +2 and a carry of 1. Is this correct or is my code wrong?
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\$\begingroup\$ I can't see what you did wrong if you don't post the code lol. \$\endgroup\$user103380– user1033802017年03月06日 04:04:08 +00:00Commented Mar 6, 2017 at 4:04
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\$\begingroup\$ Is a carry of 1 for +3 and -2 incorrect though? I created a 1 bit FA using structural modeling and then used a generate loop to generate a 4bit full adder. \$\endgroup\$John– John2017年03月06日 04:05:48 +00:00Commented Mar 6, 2017 at 4:05
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1\$\begingroup\$ Think about what a carry indicates. For instance, in an unsigned 4-bit adder, if I told you that I added 2 + 2 and got 4 + 16 = 20, would that be correct? \$\endgroup\$uint128_t– uint128_t2017年03月06日 04:31:49 +00:00Commented Mar 6, 2017 at 4:31
1 Answer 1
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For a signed adder the carry out bit has no meaning. Only the overflow bit has meaning and importance.
For +3 + (-1) you get result 2 and no overflow, which is the correct answer
(+5) + (+3) gave you +8 with overflow, also a correct answer
answered Mar 6, 2017 at 4:36
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