Why should we avoid including both blocking and unblocking assignment in same always block?

Question

Nearly all verilog books and blogs strongly suggest not to include blocking and unblocking assignment in same always block.

But sometimes I also saw some code that has both blocking and unblocking code in same block, it can still work fine in simulator.

So what is the deep reason for why not using them simultaneously ? What potential problem would be caused ?

• Sean Houlihane: As well as the correct answer below, its untidy. If you have an intent when writing code, it's easier to review if you're explicit about that intent.

Answer 1

The standard reason is that it can lead to differences in behaviour between simulation (which will do the blocking assignments in a proper 'blocking' sequential fashion) and synthesis (which will not do blocking assignments in synchronous blocks in the way you might hope).

Of course, those differences may not matter, and the design may work when synthesised anyway but you really don't want there to be any functional difference between synthesis and simulation.