Verilog code for frequency divider

Question

Can you please help me on how to create a Verilog code for frequency divider circuit that can generate 50Hz clock signal out of 50MHz signal using 16 bit synchronous counter. I have tried to do it, but it didn't work!

module divier_16 (clk_in, clk_out);
input clk_in;
wire w;
wire [0:15]temp;
output clk_out;
count_16 c1 (clk_in, w);
count_16 c2 (w, temp);
assign clk_out= temp[6];

• Eugene Sh.: Using 16 bits of what?
• Florent: And what have you tried? Could you post your code?
• Fatima: 16 bit synchronous counter
• Eugene Sh.: Can you use two of these?
• Eugene Sh.: Good. Then first divide by 1000, then divide by another 1000..

Answer 1

Unfortunately, 16 bits is not enough to convert a 50MHz signal into a 50Hz signal. This is because you need to divide the clock by 1 million. $2ドル^{16}= 65536$$ Therefore it is not nearly enough. A counter with at least 20 bits would be enough because: $2ドル^{20} = 1048576$$

To convert the signal you simply count to 1 million clock cycles, and then change the state of the output signal.

example:

always @(posedge clk_in) begin
 count_20 <= count_20 + 1;
 if(count_20 == 1000000)
 begin
 count<=0;
 clk_out <= !clk_out;
 end
end

Edit: It turns out that that ^^ would result in a 25Hz signal, so you only need to count to 500000 which needs 19 bits. The question then is where does that 20th bit come from seeing as you do need to divide by 1 million. Well, the clk_out bit serves as that 20th bit.

• Florent: another solution is to use several of those 16 bits counters. you would need at least 16 of those (16*65536 = 2²0 = 1048576)
• Makoto: I may have made a mistake, i think my solution would result in 25Hz?
• Makoto: you would only need two, that would give you 32 bits
• Anonymous: @Makoto yes, you need to count to 500_000, and second - most probably there will be warning about using different assignment type in always construct, I think you meant clk_out <= !clk_out
• Makoto: yep will change it