\$\begingroup\$
\$\endgroup\$
7
I am having a problem here can't make this code compile. It is a 4x4 keypad scanner with a 20ms debouncer. It gives error "Error: 'col' has not been declared" Any suggestion?
module keyboardScanner (input clk, input wait20, ,input [3:0] col,output reg [3:0] row, output reg [7:0] keyCode);
reg [1:0]state=2'b00;
reg [1:0]nextState=2'b00;
reg start = 0;
//state register
always@(posedge clk) begin
state <= nextState;
end
//output CL
always@(posedge clk) begin
if(start == 0)begin
case (state)
2'b00: row <= 4'b0001;
2'b01: row <= 4'b0010;
2'b10: row <= 4'b0100;
2'b11: row <= 4'b1000;
default: row <= 4'b0001;
endcase
end
if (col != 4'b0000)
start = 1;
if ((col != 4'b0000) && (wait20 == 1) && (start == 0)) begin
keyCode <= {row[1],row[2],row[3],row[0], col[0],col[1],col[2],col[3]};
start = 0;
end
end
//next state CL
always @(posedge clk) begin
if(start == 0)begin
case (state)
2'b00: nextState <= 2'b01;
2'b01: nextState <= 2'b10;
2'b10: nextState <= 2'b11;
2'b11: nextState <= 2'b00;
default: nextState <= 2'b00;
endcase
end
end
endmodule
lang-vhdl
,
) in your module declaration just before where thecol
input is declared. If you wrote it out neatly with each input/output on its own line rather than mushing everything up into one line, this would be obvious. Neat code = easy debug. \$\endgroup\$