Parallel in serial out Verilog Shift Register, odd behavior during clocking

Question

Hello I am trying to implement a parallel in serial out shift register based on the data sheet for the 74LV165A 8 bit parallel in serial out shift register74LV165A shift register schematic

the spec sheet may be found at datasheet for 74LV165A

If I make my test bench begin by shifting in serially, then try to latch data on the parallel input the data does not appear. If I begin the test bench in with parallel latch enabled then the data appears on the Q and will clock through once shifting is enabled.

My goal is to shift several sets of data through this register however currently this behavior is preventing this. Any help would be very very appreciated, event if its just a hint :)

Currently I am monitoring the set and reset information and the Q lines.

module nand3(input one, input two, input three, output out);
 assign out = !(one&two&three);
endmodule
module nand2(input one, input two, output out);
 assign out = !(one&two);
endmodule
module DFlipFlop(input clk, input reset, input D, input set, output Q);
reg Q;
initial
 Q<=0;
always @(posedge clk or negedge reset or negedge set)
begin
 if(!reset)
 Q<=0;
 else if(!set)
 Q<=1;
 else
 Q<=D;
end
endmodule
module control_mux(input [7:0]set_bits, input CP, input CE, input PL, output [16:0]bus); // bit 16 is clk, bits 15 -> 8 are set, bits 7 -> 0 of bus are reset
assign VCC = 1;
nand3 control(!CP, !CE, PL, bus[16]);
nand2 set1(!PL, set_bits[7], bus[15]);
nand2 set2(!PL, set_bits[6], bus[14]);
nand2 set3(!PL, set_bits[5], bus[13]);
nand2 set4(!PL, set_bits[4], bus[12]);
nand2 set5(!PL, set_bits[3], bus[11]);
nand2 set6(!PL, set_bits[2], bus[10]);
nand2 set7(!PL, set_bits[1], bus[9]);
nand2 set8(!PL, set_bits[0], bus[8]);
nand2 reset1(!PL, bus[15], bus[7]);
nand2 reset2(!PL, bus[14], bus[6]);
nand2 reset3(!PL, bus[13], bus[5]);
nand2 reset4(!PL, bus[12], bus[4]);
nand2 reset5(!PL, bus[11], bus[3]);
nand2 reset6(!PL, bus[10], bus[2]);
nand2 reset7(!PL, bus[9], bus[1]);
nand2 reset8(!PL, bus[8], bus[0]);
endmodule
module testbench;
 reg [7:0]set_bits;
 reg [7:0]set_bits2;
 reg CE, PL, CP, D;
 wire [16:0]bus; 
 wire [7:0]Q;
 always
 #5 CP = !CP;
 initial
 begin
 CP = 0;
 D = 0;
 set_bits = 8'b11001011;
 PL = 0; CE = 1;
 #10 PL = 1; CE = 0;
 end
 initial
 #500 $finish;
 initial
 begin
 $display("CP, CE, PL, b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0");
 $monitor("%b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b", CP, CE, PL, bus[16], bus[15], bus[14], bus[13], bus[12], bus[11], bus[10], bus[9], bus[8], bus[7], bus[6], bus[5], bus[4], bus[3], bus[2], bus[1], bus[0], Q[7], Q[6],Q[5],Q[4],Q[3],Q[2],Q[1],Q[0]);
 end
 control_mux CM(set_bits, CP, CE, PL, bus);
 DFlipFlop FF(bus[16], bus[7], D, bus[15], Q[7]);
 DFlipFlop FF2(bus[16], bus[6], Q[7], bus[14], Q[6]);
 DFlipFlop FF3(bus[16], bus[5], Q[6], bus[13], Q[5]);
 DFlipFlop FF4(bus[16], bus[4], Q[5], bus[12], Q[4]);
 DFlipFlop FF5(bus[16], bus[3], Q[4], bus[11], Q[3]);
 DFlipFlop FF6(bus[16], bus[2], Q[3], bus[10], Q[2]);
 DFlipFlop FF7(bus[16], bus[1], Q[2], bus[9], Q[1]);
 DFlipFlop FF8(bus[16], bus[0], Q[1], bus[8], Q[0]);
endmodule

Answer 1

You have misinterpreted the schematic. This line:

nand3 control(!CP, !CE, PL, bus[16]);

is in contradiction with:

• CP is active high,
• CE is active low (note the bar above the "CE" on the schematic).
• yet you use two inverted signals in the instantiation,

Also:

• the bus you think a bus is just a wire (note the connecting dots!)
• and I don't understand the control_mux concept entirely...

Now, checking out the NXP documentation, the schematic of theirs differs from what you attached.

And finally, why are you hand-instantiating gates instead of just coding up the functionality?

Like:

module sr_74LV165A (
 input DS, CP, CE_n, PL_n,
 input D0, D1, D2, D3, D4, D5, D6, D7,
 output Q7, Q7_n
);
reg [0:7] shr;
wire clk;
assign clk = CP | CE_n | !PL_n;
always @(posedge clk or negedge PL_n)
 if (!PL_n) shr <= { D0, D1, D2, D3, D4, D5, D6, D7 };
 else shr <= { DS, shr[0:6] };
assign Q7 = shr[7];
assign Q7_n = !shr[7];
endmodule

After all, this is just a shift register with parallel async load.