Trouble understanding Verilog decoder logical left shift

Question

This code is from asic-world:

module decoder_using_assign (
 binary_in , // 4 bit binary input
 decoder_out , // 16-bit out 
 enable // Enable for the decoder
);
 input [3:0] binary_in ;
 input enable ; 
 output [15:0] decoder_out ; 
 wire [15:0] decoder_out ; 
 assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule

I can't seem to wrap my head around (1 < < binary_in). binary_in is 4 bits wide, how is the logical left shift producing an output 16 bits wide when enable is true?

Answer 1

binary_in is 4 bits, so can hold a decimal value anywhere in the range 0-15.

If you left shift 1 by between 0 and 15, you get a number with at most 16 bits.

16'b0000000000000001 << 0 = 16'b0000000000000001

16'b0000000000000001 << 1 = 16'b0000000000000010

16'b0000000000000001 << 2 = 16'b0000000000000100

...

16'b0000000000000001 << 15 = 16'b1000000000000000