Help needed driving an old PIC programmer from Raspberry Pi GPIO

Question

I have been trying to use a Raspberry Pi's GPIO pins to drive an old PIC programmer board that used to have a parallel port connection before I started messing about with it.

You can see from the clip of a schematic I found online that the data write/read pin on the PIC is connected to two parallel port pins, one an output and one an input. When programming the chip, the pin flips to become an output after you send a command to read the current word.

I'm not sure in particular how reading back data from the PIC is supposed to work, because it looks to a newbie like me that the output of an inverter is connected to the input of the inverter that leads to the 'read' pin for sending data back to the PC.

Could somebody please explain what is going on at the point marked with a '?' that stops the inverter output 'fighting' with the PIC DATA pin output?

enter image description here

• Majenko: The key here is "75LS05" - google it, you'll soon fine out your answer.
• mackenir: Thanks, but having read the top couple of datasheets for the 74LS05 (not the DC-DC converter), that I'd have never realised that 'open collector' meant this behaviour.

Answer 1

The 74LS05 is an open collector inverter, therefore it can only output a logic zero on the line (sinking it to the ground), but never a logic one. The line is basically at 1 by default (because of the 10k pull-up resistors) and can be driven to zero either by the inverter output or by the PIC.

Unfortunately, the open collector nature of the 74LS05 is not explicitly indicated in the schematics (although it is possible, generally by putting an asterisk or an open-collector symbol ⎐ near the output of the gate), thus rendering it more difficult to understand.

• mackenir: Ah, so I should set 'Data Out' (pin 3 on the 74LS05) to zero when I want to read the bits coming out of 'Data In' (pin 10), right? I think this will already be the case because of how the programming protocol works...
• Ale: Exactly. If pin 3 is logic 0, pin 4 will be logic 1 (and thus high-impedance as it is open collector), thus allowing data reception via the other inverter.