i've tried a few variations but i can't make it work. here's bt_pext_u64
ah fuck it, these are only really for completeness anyway.
I found that a warmup run on the large array was necessary. perhaps some other way of pre-faulting could be done instead.
i don't think it's even that bad :)
Hmm okay there may be a bit more nuance.
Only for single pext/pdep and only for non-
IFUNC?
Let's try that explanation again.
Unfortunately yes, that's required to stop the compiler assuming pext is 3 cycles and doing it even if BMI2 is AMD's shitty pre-zen3 microcoded implementation.
i'm a bit mixed on this because i still have no idea what i'm doing with aarch64 optimisation, but i strongly suspect that the old and new code will be equivalent, at least on the vast majority of...