Add test for the s_1 variants on aarch64 & fix SVE2 BITPERM implementation #10

jepler commented 2026年03月27日 15:33:54 +01:00

a mismatch was reported for SVE2 BITPERM:

 qemu-aarch64 -U LD_PRELOAD -L /usr/aarch64-linux-gnu ./build-aarch/test/test_static
AMD64 tests: SKIP
AARCH64 tests:
support: 3e
SVE2 AES: ppp pext pdep pexts pdeps PASS
CRYPTO: ppp pext pdep pexts pdeps PASS
SVE2 BITPERM: pext pdep pexts pdeps pexts1ERROR, no match for 64 bit on iter 0, index 1:
 data: 9f6aef23cf8ad14f
 mask: 725c3868ea4a5582
 masked: 12482820ca0a5102
 portable: 3aab6f5
 test: 379b8ae2
 pdeps1ERROR, no match for 64 bit on iter 0, index 1:
 data: 390792a33c28f483
 mask: cabebfbe1aeaa5fe
 masked: 80692a21828a482
 portable: 88861e0a00e88106
 test: 780480f48060
FAIL

CRYPTO & SVE2 AES both pass so it makes me think my new test code is correct but the BITPERM implementation is wrong.

The problem appears to be that the mask has to be broadcast, and I've made a fix.

a mismatch was reported for SVE2 BITPERM: ``` qemu-aarch64 -U LD_PRELOAD -L /usr/aarch64-linux-gnu ./build-aarch/test/test_static AMD64 tests: SKIP AARCH64 tests: support: 3e SVE2 AES: ppp pext pdep pexts pdeps PASS CRYPTO: ppp pext pdep pexts pdeps PASS SVE2 BITPERM: pext pdep pexts pdeps pexts1ERROR, no match for 64 bit on iter 0, index 1: data: 9f6aef23cf8ad14f mask: 725c3868ea4a5582 masked: 12482820ca0a5102 portable: 3aab6f5 test: 379b8ae2 pdeps1ERROR, no match for 64 bit on iter 0, index 1: data: 390792a33c28f483 mask: cabebfbe1aeaa5fe masked: 80692a21828a482 portable: 88861e0a00e88106 test: 780480f48060 FAIL ``` CRYPTO & SVE2 AES both pass so it makes me think my new test code is correct but the BITPERM implementation is wrong. The problem appears to be that the `mask` has to be broadcast, and I've made a fix.

jjl commented 2026年03月27日 15:42:28 +01:00

there are versions for a mask vector and a mask scalar and either i'm reading the docs wrong or there's something funkier than that going on. maybe try the explicit _n_u<size> suffix to figure out what's going on?

https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=bext

there are versions for a mask vector and a mask scalar and either i'm reading the docs wrong or there's something funkier than that going on. maybe try the explicit `_n_u<size>` suffix to figure out what's going on? https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=bext

jepler commented 2026年03月27日 15:53:41 +01:00

If you approve the workflow to run you will hopefully see that it is fixed. (but you'd have to test the intermediate commit locally to see that it really was broken...)

If you approve the workflow to run you will hopefully see that it is fixed. (but you'd have to test the intermediate commit locally to see that it really was broken...)

jjl commented 2026年03月27日 16:29:56 +01:00

You should be approved for your PRs to run automatically now.

It's your last PR where you changed it to take &mask. &mask will indeed likely be a uint64_t. That's why the scalar version doesn't work anymore.

You should be approved for your PRs to run automatically now. It's your last PR where you changed it to take &mask. &mask will indeed likely be a uint64_t. That's why the scalar version doesn't work anymore.

jepler commented 2026年03月27日 16:47:13 +01:00

oh yeah, I see now that the s_1 functions are the ones I previously touched, without understanding that they were not being tested. So I "fixed" the compiler error in 1493d18540 but nothing was verifying the functionality.

Once I added s_1 tests, they failed, which is good news because my change was nonsense: it was loading m with &mask[0], &mask[1], ... up to the vector size, except that of course &mask[1] is nonsense. https://dougallj.github.io/asil/doc/ld1d_z_p_br_64.html

I think the new change is correct: It loads mask once and broadcasts it into all the 64-bit lanes of the sve register. https://dougallj.github.io/asil/doc/dup_z_r_64.html

oh yeah, I see now that the `s_1` functions are the ones I previously touched, without understanding that they were not being tested. So I "fixed" the compiler error in 1493d18540e2eb49218d550f5a6318f1e48507ec but nothing was verifying the functionality. Once I added `s_1` tests, they failed, which is good news because my change was nonsense: it was loading `m` with `&mask[0]`, `&mask[1]`, ... up to the vector size, except that of course `&mask[1]` is nonsense. https://dougallj.github.io/asil/doc/ld1d_z_p_br_64.html I think the new change is correct: It loads mask once and broadcasts it into all the 64-bit lanes of the sve register. https://dougallj.github.io/asil/doc/dup_z_r_64.html

jjl commented 2026年03月27日 17:18:14 +01:00

i'm a bit mixed on this because i still have no idea what i'm doing with aarch64 optimisation, but i strongly suspect that the old and new code will be equivalent, at least on the vast majority of kit, so what the hell 🤷

i'm a bit mixed on this because i still have no idea what i'm doing with aarch64 optimisation, but i strongly suspect that the old and new code will be equivalent, at least on the vast majority of kit, so what the hell 🤷