• About
• PQC
• LWC
• CAESAR
• SHA-3
• Minerva
• ATHENa
• CAESAR Results >
  • FPGA: Rankings
  • FPGA: All Results
• SHA-3 Results >
  • FPGA: Rankings
  • FPGA: All Results
  • ASIC: Rankings
  • ASIC: All Results
• Presentations
• Publications
• Standards
• Specifications
• Contact Us

Hardware Benchmarking of CAESAR Candidates

• CAESAR: Competition for Authenticated Encryption: Security, Applicability, and Robustness

• Benchmarking of Round 3 CAESAR Candidates in Hardware: Methodology, Designs & Results - Power Point presentation (last revised on August 28, 2017)
  [history of updates, previous versions]

• Benchmarking of Round 3 CAESAR Candidates in Hardware: Appendix - New Implementations of AES-OTR, CLOC, & SILC - Power Point presentation (based on the status of the ATHENa Database of Results as of November 11, 2017)

• VHDL/Verilog Code of CAESAR Candidates: Summary I (last revised on August 26, 2017)

• VHDL/Verilog Code of CAESAR Candidates: Summary II (last revised on August 26, 2017)

• ATHENa Database of Results: Rankings View

• ATHENa Database of Results: Table View

• Toward a New HLS-Based Methodology for FPGA Benchmarking of Candidates in Cryptographic Competitions: The CAESAR Contest Case Study - presentation at FPT 2017

• Benchmarking of Round 2 CAESAR Candidates in Hardware: Methodology, Designs & Results - Power Point presentation (last revised on August 11, 2016)
  [history of updates, previous versions]

• Toward Fair and Comprehensive Benchmarking of CAESAR Candidates in Hardware: Standard API, High-Speed Implementations in VHDL/Verilog, and Benchmarking Using FPGAs - presentation at DIAC 2016

• Enhancing CAESAR Hardware API Support for Lightweight Architectures - presentation at DIAC 2016

• An Alternative Approach to Hardware Benchmarking of CAESAR Candidates Based on the Use of High-Level Synthesis Tools - presentation at DIAC 2016

GMU Implementations of Authenticated Ciphers and Their Building Blocks

• GMU Source Code of Round 3 & Round 2 CAESAR Candidates, AES-GCM, AES, and Keccak Permutation F (last revised on February 20, 2019)

• AES: Symbols, Block Diagrams, ASM Charts (posted on June 30, 2015)

• Keccak Permutation F: Symbols, Block Diagrams, ASM Charts (posted on June 30, 2015)

CAESAR Hardware API v1.0

• Documentation:

• CAESAR Hardware API, full specification, v1.0 (last revised on May 12, 2016; posted on ePrint on June 17, 2016)

• Addendum to the CAESAR Hardware API v1.0 (last revised on June 10, 2016)

• Implementer's Guide to Hardware Implementations Compliant with the CAESAR Hardware API, v2.0 (last revised on December 5, 2017)

• Verilog/VHDL Code: Suggested List of Deliverables, v1.0 (posted on June 20, 2016)

• Rules for Reduced Complexity Block Diagrams, by William Diehl, v1.0 (posted on June 20, 2016)

• Code:

• Development Package for Hardware Implementations Compliant with the CAESAR Hardware API, v2.0 (last revised on December 5, 2017) [history of updates, previous releases]

GMU Hardware API v1.2 (superseded by CAESAR Hardware API v1.0)

• Documentation:

• GMU Hardware API for Authenticated Ciphers, full specification (last revised on December 6, 2015)

• GMU Hardware API for Authenticated Ciphers, presentation at DIAC 2015, Singapore, September 28-29, 2015 (posted on September 29, 2015)

• Code:

• Supporting Files for High-Speed Implementations v1.2 (last revised on December 6, 2015)