Pull requests: chipsalliance/yosys-f4pga-plugins

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Pull requests list

Adding missing tcl.h includes

#554 opened Jan 8, 2025 by dpetrisko

reversed ranges

#532 opened Jun 19, 2023 by wsipak • Draft

antmicro/yosys-systemverilog#1743: Compensate for chipsalliance/Surelog#3670

#522 opened May 30, 2023 by hs-apotell

Check for typedefs before calculating width

#505 opened May 8, 2023 by wsipak • Draft

XDC: Add missing OBUFT primitive

#494 opened Apr 25, 2023 by hannesha

systemverilog-plugin: add parameter type propagation through hierarchy

#469 opened Mar 17, 2023 by joennlae

systemverilog-plugin: fix handling large constants

#465 opened Mar 6, 2023 by kamilrakoczy • Draft

CI: check different Yosys versions

#445 opened Jan 24, 2023 by apokusinski

Parmys (Partial Mapper for Yosys) plugin

#421 opened Dec 15, 2022 by poname

ql-qlf: k6n10f: Update QL_DSP2/QL_DSP3 logic

#393 opened Oct 28, 2022 by robertszczepanski

foreach loop support

#384 opened Sep 27, 2022 by mglb • Draft

[k6n10f] Remove superfluous cell models

#371 opened Jul 21, 2022 by mkurc-ant

Arith-stats plugin

#352 opened Jun 15, 2022 by tcal-x • Draft

🔄 Synced file(s) with SymbiFlow/symbiflow-common-config

#219 opened Feb 9, 2022 by common-config-bot • Draft

Adds class struct variable support.

#212 opened Feb 4, 2022 by QuantamHD

WIP: [SDC plugin] Improve error messages

#181 opened Dec 31, 2021 by tmichalak

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Pull requests: chipsalliance/yosys-f4pga-plugins

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Pull requests list