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NEWS for Gnucap. Each snapshot corresponds to a tag in the git repository and
associated tarball. This file summarizes the important changes.
== 20250***-dev
- refactor matrix and interface
- request inodes explicitly
- store footprint, not just spike size
- cbs improvements
- make node order pluggable, trace order plugin
- move to c++14 (due to modelgen-verilog)
- default to case sensitive, c.f. README
- ..
== 20250731-dev
- refactor ELEMENT commons
- indexed parameter assignments
- drop extra node from coupled inductor
- switch internal temperature to Kelvin
- hierarchical $temperature, $dtemp etc.
- per-device integration method selection
- stash unknown system parameters
- provide mempcpy for non-glibc systems
- random seed
- Verilog-AMS $rdist_* functions
- asymmetric and smaller matrix footprint
- bugfix net_decl parse
- bugfix "delete" parse
== 20250525-dev
- predictor for node voltages
- support same_port device aka "net"
- ground and .ground statement
- add build preset for afl; afl related fixes
- fold in d_subckt.cc from mg-vams
- move deflate call to CARD_LIST::expand
- port directions and type declarations
- provide CS::getline following STL convention
- drop termcap from default build, better override
- fix gaps in port connections, floating ports
- fix module instanciation in spice
- fix port names in subcircuits instanciated using 'X'
- build fix: propagate make errors in subdirs
== 20250301-dev
- arbitrary number of module ports
- leave optional unconnected ports floating
- print debug message on dtmin change
- delay argument in logic primitive
- fix: quoted strings in parameter values
- fix: purge node attributes before deletion
- cleanup modelgen precalc_last
- reverse parameter indexing (now forward)
- current ports are just ports
- ac analysis: avoid pre-schedule hack
- NODE is now CARD
- indirect storage for owner/scope
- debug aid: cover matrix numbers/stats in tests
== 20241210-dev
- matrix interface & cbs test
- public COMMON_LOGIC, and fix a logic bug
- `include: now relative to current file
- virtual portlists: CARD::n_
- inherit attributes in copy
== 20241031-dev
- support named port syntax
- escaped identifiers for ports
- interoperability with spice port names
- real, integer, string parameters in verilog
- verilog compliant division and log
- finish hooks in devices
== 20241002-dev
- quantize time in tr_swp
- reschedule pruned events
- event owner
- longer double in lu decomp
- fix oversight in vsvs advance
- "module" alias for "subckt"
- avoid global _nstat use
- simplify configure invocation
== 20240702-dev
- fix trace header for use in C
- hierarchical system params
- noise_num: device interface
- matrix: eliminate edge vectors
- refactored port & parameter attribute
- avoid copy in set_param_by_name
- new build system
== 20240430-dev
- add noise to sim_data
- code of conduct
- fixes for spice_wrapper
- drop spice_wrapper (moved to models repo)
== 20240331-dev
- fix a bug in transient QA
- improve trln ac formulation
- hotfix commons clash
- explicit attribute list assignment op
- add CONTRIBUTE
== 20240220
- prepare build system files for use in extension packages
- support for directories in attach plugin
- Tokenize Verilog-AMS arrays
- local search for gnucap.rc, see manual
- Library improvements related to Verilog-AMS
== development snapshot 20231131
- instanciate logic devices using any language
- VAMS LRM compliant logic device ports
== development snapshot 20231031
- attribute instance
== development snapshot 20230930
- revisit resistor short condition handling
- fix uninitialised access in getlines
- fix a mem leak in ternary op
- add CS::reset_fail
- parse string in angle brackets
== development snapshot 20230729
- white space in quoted strings
- escaped chars in quoted strings
- more testing and interactive testing
- typed NOT_INPUT override
- version presented at fsic23
== development snapshot 20230623
This is a development snapshot addressing expression handling.
- ternary operator
- modulo binary operator
- quoted strings
== development snapshot 20230520
- param eval recursion bugfix
- allow '$' in identifiers
- add man pages from Debian
== development snapshot 20230214
This snapshot relates to new Verilog-AMS work.
- module overloading interface
- allow '$' in identifiers
- explicitly specify c++11 during build
- move COMPONENT::_value to ELEMENT
- ELEMENT cleanup and parameter sweeps
- "override" decorators
- more scope flexibility in commands
- fix case insensitivity in label compare
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