gnucap.git - Gnu Circuit Analysis Package

diff --git a/apps/lang_verilog.cc b/apps/lang_verilog.cc
index e78ae47d..0fd554ca 100644
--- a/apps/lang_verilog.cc
+++ b/apps/lang_verilog.cc

@@ -824,8 +824,14 @@ void LANG_VERILOG::print_args(OMSTREAM& o, const COMPONENT* x)

if (x->param_is_printable(ii)) {

o << sep;

print_attributes(o, x->param_id_tag(ii));

- o << '.' << x->param_name(ii) << '(' << x->param_value(ii) << ')';

- sep = ',';

+ std::string pn = x->param_name(ii);

+ if(pn==""){ untested();

+ o << x->param_value(ii);

+ sep = ", ";

+ }else{

+ o << '.' << x->param_name(ii) << '(' << x->param_value(ii) << ')';

+ sep = ',';

+ }

}else{

}

}

diff --git a/lib/e_card.cc b/lib/e_card.cc
index 7016ec2b..0ca75d4d 100644
--- a/lib/e_card.cc
+++ b/lib/e_card.cc

@@ -221,7 +221,7 @@ const CARD* CARD::find_in_parent_scope(const std::string& name)const

CARD_LIST::const_iterator j = i;

if (i == p_scope->end()) {

throw Exception_Cant_Find(long_label(), name);

- }else if(p_scope->find_again(name, ++j) != p_scope->end()){ untested();

+ }else if(p_scope->find_again(name, ++j) != p_scope->end()){

error(bWARNING, "duplicate match " + name + " in " + long_label() + "\n");

}else{

}

diff --git a/tests/==out/d_subckt.3.gc.out b/tests/==out/d_subckt.3.gc.out
index 90261e78..5b4d6669 100644
--- a/tests/==out/d_subckt.3.gc.out
+++ b/tests/==out/d_subckt.3.gc.out

@@ -13,7 +13,7 @@ V1 ( 2 0 ) DC 1.

X1 ( 2 1 3 ) zzz

X2 ( 2 4 5 ) zzz

.subckt zzz ( 1 2 4 )

-ground 0円 ;

+.ground 0円 ;

R1 ( 1 2 ) 1.

R2 ( 2 0 ) 1.

R3 ( 2 3 ) 1.