最近在工程中,需要用Verilog对VHDL模块进行仿真,VHDL端口中含有二维数组,在Verilog中怎么例化

VHDL模块声明:

entity dma_mod is
generic(RX_NUM :integer:=2);
port (
activing: in std_logic_vector((RX_NUM-1) downto 0);
clk_80m : in std_logic;
dma_len : in ARRAY16((RX_NUM-1) downto 0); --2X16
rd_jump : in ARRAY10((RX_NUM-1) downto 0);
rd_addr : out std_logic_vector(9 downto 0);
rd_data : in ARRAY17((RX_NUM-1) downto 0);
pcie_clk: in std_logic;
iec2dma : out std_logic_vector(46 downto 0);
dma2iec : in std_logic_vector(2 downto 0);
dma_ok : out std_logic_vector(15 downto 0);
dma_all : out std_logic_vector(15 downto 0);
dma_fail: out std_logic_vector(15 downto 0);
dma_rst : out std_logic_vector(15 downto 0);
err_num : out std_logic_vector(3 downto 0)
);
end dma_mod;

-----------------------------------------------------

wire [15:0] dma_len [1:0] ;
wire [9 :0] rd_jump [1:0] ;
wire [9 :0] rd_addr ;
wire [16:0] rd_data [1:0] ;

dma_mod u1(
.activing (2'b11 ) ,
.clk_80m (clk ) ,

.dma_len (dma_len ) ,
.rd_jump (rd_jump ) ,
.rd_addr (rd_addr ) ,
.rd_data (rd_data ) ,

.pcie_clk (clk ) ,
.iec2dma ( ) ,
.dma2iec ( ) ,
.dma_ok ( ) ,
.dma_all ( ) ,
.dma_fail ( ) ,
.dma_rst ( ) ,
.err_num ( )
);


assign dma_len[0] = 16'h000A ;
assign dma_len[1] = 16'h000A ;

assign rd_jump[1] = 10'h000 ;
assign rd_data[1] = 17'h00000 ;

仿真会报错 ERROR: [VRFC 10-394] cannot access memory dma_len directly ,

怎么解决这个问题? help