The MIPS CPU architecture is used in computer architectures like SGI O2 and Octane systems, Nintendo N64 as well as the Sony Playstation, Playstation 2 and Playstation Portable.
General Registers
| Name
|
Number
|
Function
|
Callee must preserve?
|
| $zero
|
0ドル
|
constant 0
|
n/a
|
| $at
|
1ドル
|
assembler temporary
|
no
|
| $v0–$v1
|
2ドル–3ドル
|
values for function returns and expression evaluation
|
no
|
| $a0–$a3
|
4ドル–7ドル
|
function arguments
|
no
|
| $t0–$t7
|
8ドル–15ドル
|
temporaries
|
no
|
| $s0–$s7
|
16ドル–23ドル
|
saved temporaries
|
yes
|
| $t8–$t9
|
24ドル–25ドル
|
temporaries
|
no
|
| $k0–$k1
|
26ドル–27ドル
|
reserved for OS kernel
|
no
|
| $gp
|
28ドル
|
global pointer
|
yes
|
| $sp
|
29ドル
|
stack pointer
|
yes
|
| $fp/$s8
|
30ドル
|
frame pointer
|
yes
|
| $ra
|
31ドル
|
return address
|
n/a
|
Note: All except registers on the MIPS except $zero, HI and LO are general registers; the listed usage is per convention and not enforced by the processor or the assembler. The register name $s8 is a synonym for $fp used in some assemblers, in systems where the frame pointer is not regularly used.
Arithmetic Registers
| Register
|
Multiplication
|
Division
|
| HI
|
Multiplicand Upper word
|
Quotient
|
| LOW
|
Multiplicand Lower word
|
Remainder
|
Coprocessor 0 Registers
| Name
|
Number
|
Function
|
Callee must preserve?
|
| c0_index
|
cop0 0ドル
|
TLB entry index register
|
n/a
|
| c0_random
|
cop0 1ドル
|
TLB randomized access register
|
n/a
|
| c0_entrylo
|
cop0 2ドル
|
Low-order word of "current" TLB entry
|
n/a
|
| c0_context
|
cop0 4ドル
|
Page-table lookup address
|
n/a
|
| c0_vaddr
|
cop0 8ドル
|
Virtual address associated with certain exceptions
|
n/a
|
| c0_entryhi
|
cop0 10ドル
|
High-order word of "current" TLB entry
|
n/a
|
| c0_status
|
cop0 12ドル
|
Processor status register
|
n/a
|
| c0_cause
|
cop0 13ドル
|
Exception cause register
|
n/a
|
| c0_epc
|
cop0 14ドル
|
PC at which exception occurred
|
n/a
|
Instruction fields
| Field
|
Size
|
Position
|
Op Types
|
Description
|
| op
|
6
|
26-31
|
R, I, J
|
opcode for the instruction or group of instructions.
|
| rs
|
5
|
21-25
|
R, I
|
Source register for store operations, destination for all other operations.
|
| rt
|
5
|
16-20
|
R, I
|
First operand register.
|
| rd
|
5
|
11-15
|
R
|
Second operand register.
|
| shift
|
5
|
6-10
|
R
|
Immediate operand for shift and rotate instructions.
|
| func
|
6
|
0-5
|
R
|
Extended opcode.
|
| imm
|
16
|
0-15
|
I
|
Half-word immediate operand.
|
| address
|
0-25
|
J
|
26-bit address field for unconditional jump operations.
|
Addressing modes
| Type
|
Assembly Format
|
Opcode format
|
Comments
|
| Register
|
inst rs, rd, rt
|
op rs, rd, rt, shift, func
|
The opcode represents a group of operations rather than a specific instruction; the func field contains the actual operation. The shift field is only used in shift and rotate operations.
|
| Immediate (I-type)
|
inst rs, rt, imm
|
opcode rs, rt, imm
|
Immediate operation use a 16-bit immediate value from the instruction word itself.
|
| Load (I-type)
|
inst rs, imm(rt)
|
op rs, rt, imm
|
Load/Store operations are a special case of immediate, where the offset is the immediate operand.
|
| Store (I-type)
|
inst rs, offset(rt)
|
op rs, rt, imm
|
Unlike in most other operations, the rs register is the data source.
|
| Cond. Branch(I-type)
|
inst rs, rt, label
|
op rs, rt, imm
|
Conditional branches have a 16-bit relative range.
|
| Jump {J-type)
|
inst label
|
op address
|
the J and JAL operations have a 26-bit relative range.
|
Note: The assembly formats given are those from the official MIPS Technologies documentation. Other assemblers (e.g., gas) may use different formats.
See Also
Articles
References
