1 /* $NetBSD: intr.h,v 1.7 2024年11月19日 08:28:01 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _RISCV_INTR_H_ 33#define _RISCV_INTR_H_ 34 35#ifdef _KERNEL_OPT 36#include "opt_multiprocessor.h" 37#endif 38 39 /* 40 * This is a common <machine/intr.h> for all RISCV platforms. 41 */ 42 43#define IPL_NONE 0 44#define IPL_SOFTCLOCK (IPL_NONE + 1) 45#define IPL_SOFTBIO (IPL_SOFTCLOCK + 1) 46#define IPL_SOFTNET (IPL_SOFTBIO + 1) 47#define IPL_SOFTSERIAL (IPL_SOFTNET + 1) 48#define IPL_VM (IPL_SOFTSERIAL + 1) 49#define IPL_SCHED (IPL_VM + 1) 50 //#define IPL_DDB (IPL_SCHED + 1) 51#define IPL_HIGH (IPL_SCHED + 1) 52 53#define IPL_SAFEPRI IPL_SOFTSERIAL 54 55#define _IPL_N (IPL_HIGH + 1) 56 57#if 0 58#define _IPL_NAMES(pfx) { pfx "none", pfx "softclock/bio", pfx "softnet/serial", \ 59 pfx "vm", pfx "sched", pfx "ddb", pfx "high" } 60#endif 61 62#define IST_UNUSABLE -1 /* interrupt cannot be used */ 63#define IST_NONE 0 /* none (dummy) */ 64#define IST_PULSE 1 /* pulsed */ 65#define IST_EDGE 2 /* edge-triggered */ 66#define IST_LEVEL 3 /* level-triggered */ 67#define IST_LEVEL_HIGH 4 /* level triggered, active high */ 68#define IST_LEVEL_LOW 5 /* level triggered, active low */ 69#define IST_MPSAFE 0x100 70 71#define IPI_NOP 0 /* do nothing, interrupt only */ 72#define IPI_AST 1 /* force ast */ 73#define IPI_KPREEMPT 2 /* schedule a kernel preemption */ 74#define IPI_SUSPEND 3 /* DDB suspend signaling */ 75#define IPI_HALT 4 /* halt cpu */ 76#define IPI_XCALL 5 /* xcall */ 77#define IPI_GENERIC 6 /* generic IPI */ 78#define NIPIS 7 79 80#ifdef __INTR_PRIVATE 81#if 0 82 struct splsw { 83 int (*splsw_splhigh)(void); 84 int (*splsw_splsched)(void); 85 int (*splsw_splvm)(void); 86 int (*splsw_splsoftserial)(void); 87 int (*splsw_splsoftnet)(void); 88 int (*splsw_splsoftbio)(void); 89 int (*splsw_splsoftclock)(void); 90 int (*splsw_splraise)(int); 91 void (*splsw_spl0)(void); 92 void (*splsw_splx)(int); 93 int (*splsw_splhigh_noprof)(void); 94 void (*splsw_splx_noprof)(int); 95 int (*splsw_splintr)(uint32_t *); 96 void (*splsw_splcheck)(void); 97}; 98 99 struct ipl_sr_map { 100 uint32_t sr_bits[_IPL_N]; 101}; 102#endif 103#else 104 struct splsw; 105#endif /* __INTR_PRIVATE */ 106 107 typedef int ipl_t; 108 typedef struct { 109 ipl_t _spl; 110} ipl_cookie_t; 111 112#ifdef _KERNEL 113 114#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS) 115#define __HAVE_PREEMPTION 1 116#define SOFTINT_KPREEMPT (SOFTINT_COUNT+0) 117#endif 118 119#ifdef __INTR_PRIVATE 120#if 0 121 extern struct splsw cpu_splsw; 122#endif 123 extern struct ipl_sr_map ipl_sr_map; 124#endif /* __INTR_PRIVATE */ 125 126 int splhigh(void); 127 int splhigh_noprof(void); 128 int splsched(void); 129 int splvm(void); 130 int splsoftserial(void); 131 int splsoftnet(void); 132 int splsoftbio(void); 133 int splsoftclock(void); 134 int splraise(int); 135 void splx(int); 136 void splx_noprof(int); 137 void spl0(void); 138 int splintr(unsigned long *); 139 140 void softint_deliver(void); 141 142 struct cpu_info; 143 144#define ENABLE_INTERRUPTS() csr_sstatus_set(SR_SIE) 145 146#define DISABLE_INTERRUPTS() csr_sstatus_clear(SR_SIE) 147 148 void ipi_init(struct cpu_info *); 149 void ipi_process(struct cpu_info *, unsigned long); 150 151 int riscv_ipi_intr(void *arg); 152 153 /* 154 * These make no sense *NOT* to be inlined. 155 */ 156 static inline ipl_cookie_t 157 makeiplcookie(ipl_t s) 158{ 159 return (ipl_cookie_t){._spl = s}; 160} 161 162 static inline int 163 splraiseipl(ipl_cookie_t icookie) 164{ 165 return splraise(icookie._spl); 166} 167 168 void *intr_establish(int, int, int, int (*)(void *), void *); 169 void *intr_establish_xname(int, int, int, int (*)(void *), void *, const char *); 170 void intr_disestablish(void *); 171 172#endif /* _KERNEL */ 173#endif /* _RISCV_INTR_H_ */ 174