Pass by name for macro arguments

Question

For functions, we can use pass by name as below:

 function void xyz(string x,int y);
 $display(x,,y);
 endfunction
 initial begin
 xyz(.x("Hi"),.y(2));
 end

Now, I have a macro like below:

 `define XYZ(name,number) \
 int num; \
 num=number; \
 $display("%s %d",``name``,num);

It is invoked as XYZ(hi,2). I would like to know how I can use pass by name in macros just as we do for functions.

Answer 1

A macro in verilog (also in c/c++) is a mechanism which allows simple text manipulations. It does text substitutions before any syntactic checking by the compiler. Arguments in macros are substituted with their actual values in text without any analysis. So, in your case the instance of `XYZ(hi,2) will just be expanded as

int num; \
 num=2; \
 $display("%s %d",hi,num);

This not what will work if you want to see the name printed with $display. However, there are ways to stingize arguments. For that you need to change the definition syntax to the following:

`define XYZ(name,number) \
 int num; \
 num=number; \
 $display("%s %d",`"name`",num); // `"name" should also work
`XYZ(hi,2)
--->
 int num;
 num=2;
 $display("%s %d","hi",num);

Answer 2

I would like to know how I can use pass by name in macros just as we do for functions.

You can not use pass-by-name for define macros like you do for functions. You can not do something like this:

`XYZ(.name(hi),.number(2))

Refer to IEEE Std 1800-2017, section 22.5.1 `define. This shows the complete supported syntax for macros with several examples.