LLVM: lib/Target/RISCV/RISCVTargetMachine.cpp Source File

LLVM 22.0.0git
RISCVTargetMachine.cpp
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1//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISC-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
14#include "MCTargetDesc/RISCVBaseInfo.h"
15#include "RISCV.h"
16#include "RISCVMachineFunctionInfo.h"
17#include "RISCVTargetObjectFile.h"
18#include "RISCVTargetTransformInfo.h"
19#include "TargetInfo/RISCVTargetInfo.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
22#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
23#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24#include "llvm/CodeGen/GlobalISel/Legalizer.h"
25#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
26#include "llvm/CodeGen/MIRParser/MIParser.h"
27#include "llvm/CodeGen/MIRYamlMapping.h"
28#include "llvm/CodeGen/MachineScheduler.h"
29#include "llvm/CodeGen/MacroFusion.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/RegAllocRegistry.h"
32#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
33#include "llvm/CodeGen/TargetPassConfig.h"
34#include "llvm/InitializePasses.h"
35#include "llvm/MC/TargetRegistry.h"
36#include "llvm/Passes/PassBuilder.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Target/TargetOptions.h"
39#include "llvm/Transforms/IPO.h"
40#include "llvm/Transforms/Scalar.h"
41#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
42#include <optional>
43using namespace llvm;
44
45 static cl::opt<bool> EnableRedundantCopyElimination(
46 "riscv-enable-copyelim",
47 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
48 cl::Hidden);
49
50// FIXME: Unify control over GlobalMerge.
51static cl::opt<cl::boolOrDefault>
52 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
53 cl::desc("Enable the global merge pass"));
54
55static cl::opt<bool>
56 EnableMachineCombiner("riscv-enable-machine-combiner",
57 cl::desc("Enable the machine combiner pass"),
58 cl::init(true), cl::Hidden);
59
60 static cl::opt<unsigned> RVVVectorBitsMaxOpt(
61 "riscv-v-vector-bits-max",
62 cl::desc("Assume V extension vector registers are at most this big, "
63 "with zero meaning no maximum size is assumed."),
64 cl::init(0), cl::Hidden);
65
66 static cl::opt<int> RVVVectorBitsMinOpt(
67 "riscv-v-vector-bits-min",
68 cl::desc("Assume V extension vector registers are at least this big, "
69 "with zero meaning no minimum size is assumed. A value of -1 "
70 "means use Zvl*b extension. This is primarily used to enable "
71 "autovectorization with fixed width vectors."),
72 cl::init(-1), cl::Hidden);
73
74 static cl::opt<bool> EnableRISCVCopyPropagation(
75 "riscv-enable-copy-propagation",
76 cl::desc("Enable the copy propagation with RISC-V copy instr"),
77 cl::init(true), cl::Hidden);
78
79 static cl::opt<bool> EnableRISCVDeadRegisterElimination(
80 "riscv-enable-dead-defs", cl::Hidden,
81 cl::desc("Enable the pass that removes dead"
82 " definitions and replaces stores to"
83 " them with stores to x0"),
84 cl::init(true));
85
86static cl::opt<bool>
87 EnableSinkFold("riscv-enable-sink-fold",
88 cl::desc("Enable sinking and folding of instruction copies"),
89 cl::init(true), cl::Hidden);
90
91static cl::opt<bool>
92 EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden,
93 cl::desc("Enable the loop data prefetch pass"),
94 cl::init(true));
95
96 static cl::opt<bool> DisableVectorMaskMutation(
97 "riscv-disable-vector-mask-mutation",
98 cl::desc("Disable the vector mask scheduling mutation"), cl::init(false),
99 cl::Hidden);
100
101static cl::opt<bool>
102 EnableMachinePipeliner("riscv-enable-pipeliner",
103 cl::desc("Enable Machine Pipeliner for RISC-V"),
104 cl::init(false), cl::Hidden);
105
143}
144
145 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
146 return RM.value_or(Reloc::Static);
147}
148
150 StringRef CPU, StringRef FS,
151 const TargetOptions &Options,
152 std::optional<Reloc::Model> RM,
153 std::optional<CodeModel::Model> CM,
154 CodeGenOptLevel OL, bool JIT)
156 T, TT.computeDataLayout(Options.MCOptions.getABIName()), TT, CPU, FS,
158 getEffectiveCodeModel(CM, CodeModel::Small), OL),
159 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
160 initAsmInfo();
161
162 // RISC-V supports the MachineOutliner.
163 setMachineOutliner(true);
165
166 // RISC-V supports the debug entry values.
168
169 if (TT.isOSFuchsia() && !TT.isArch64Bit())
170 report_fatal_error("Fuchsia is only supported for 64-bit");
171
172 setCFIFixup(true);
173}
174
175const RISCVSubtarget *
177 Attribute CPUAttr = F.getFnAttribute("target-cpu");
178 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
179 Attribute FSAttr = F.getFnAttribute("target-features");
180
181 std::string CPU =
182 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
183 std::string TuneCPU =
184 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
185 std::string FS =
186 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
187
188 unsigned RVVBitsMin = RVVVectorBitsMinOpt;
189 unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
190
191 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
192 if (VScaleRangeAttr.isValid()) {
193 if (!RVVVectorBitsMinOpt.getNumOccurrences())
194 RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
195 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
196 if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
197 RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
198 }
199
200 if (RVVBitsMin != -1U) {
201 // FIXME: Change to >= 32 when VLEN = 32 is supported.
202 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
203 isPowerOf2_32(RVVBitsMin))) &&
204 "V or Zve* extension requires vector length to be in the range of "
205 "64 to 65536 and a power 2!");
206 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
207 "Minimum V extension vector length should not be larger than its "
208 "maximum!");
209 }
210 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
211 isPowerOf2_32(RVVBitsMax))) &&
212 "V or Zve* extension requires vector length to be in the range of "
213 "64 to 65536 and a power 2!");
214
215 if (RVVBitsMin != -1U) {
216 if (RVVBitsMax != 0) {
217 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
218 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
219 }
220
221 RVVBitsMin = llvm::bit_floor(
222 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
223 }
224 RVVBitsMax =
225 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
226
228 raw_svector_ostream(Key) << "RVVMin" << RVVBitsMin << "RVVMax" << RVVBitsMax
229 << CPU << TuneCPU << FS;
230 auto &I = SubtargetMap[Key];
231 if (!I) {
232 // This needs to be done before we create a new subtarget since any
233 // creation will depend on the TM and the code generation flags on the
234 // function that reside in TargetOptions.
236 auto ABIName = Options.MCOptions.getABIName();
237 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
238 F.getParent()->getModuleFlag("target-abi"))) {
239 auto TargetABI = RISCVABI::getTargetABI(ABIName);
240 if (TargetABI != RISCVABI::ABI_Unknown &&
241 ModuleTargetABI->getString() != ABIName) {
242 report_fatal_error("-target-abi option != target-abi module flag");
243 }
244 ABIName = ModuleTargetABI->getString();
245 }
246 I = std::make_unique<RISCVSubtarget>(
247 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
248 }
249 return I.get();
250}
251
258
259TargetTransformInfo
261 return TargetTransformInfo(std::make_unique<RISCVTTIImpl>(this, F));
262}
263
264// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
265// for all memory accesses, so it is reasonable to assume that an
266// implementation has no-op address space casts. If an implementation makes a
267// change to this, they can override it here.
269 unsigned DstAS) const {
270 return true;
271}
272
273ScheduleDAGInstrs *
275 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
277
278 if (ST.enableMISchedLoadClustering())
279 DAG->addMutation(createLoadClusterDAGMutation(
280 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
281
282 if (ST.enableMISchedStoreClustering())
283 DAG->addMutation(createStoreClusterDAGMutation(
284 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
285
286 if (!DisableVectorMaskMutation && ST.hasVInstructions())
287 DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
288
289 return DAG;
290}
291
292ScheduleDAGInstrs *
294 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
296
297 if (ST.enablePostMISchedLoadClustering())
298 DAG->addMutation(createLoadClusterDAGMutation(
299 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
300
301 if (ST.enablePostMISchedStoreClustering())
302 DAG->addMutation(createStoreClusterDAGMutation(
303 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
304
305 return DAG;
306}
307
308namespace {
309
310class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
311public:
312 RVVRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
313 : RegisterRegAllocBase(N, D, C) {}
314};
315
316static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
317 const MachineRegisterInfo &MRI,
318 const Register Reg) {
319 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
320 return RISCVRegisterInfo::isRVVRegClass(RC);
321}
322
323static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
324
325static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;
326
327/// -riscv-rvv-regalloc=<fast|basic|greedy> command line option.
328/// This option could designate the rvv register allocator only.
329/// For example: -riscv-rvv-regalloc=basic
330static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,
331 RegisterPassParser<RVVRegisterRegAlloc>>
332 RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,
333 cl::init(&useDefaultRegisterAllocator),
334 cl::desc("Register allocator to use for RVV register."));
335
336static void initializeDefaultRVVRegisterAllocatorOnce() {
337 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
338
339 if (!Ctor) {
340 Ctor = RVVRegAlloc;
341 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);
342 }
343}
344
345static FunctionPass *createBasicRVVRegisterAllocator() {
346 return createBasicRegisterAllocator(onlyAllocateRVVReg);
347}
348
349static FunctionPass *createGreedyRVVRegisterAllocator() {
350 return createGreedyRegisterAllocator(onlyAllocateRVVReg);
351}
352
353static FunctionPass *createFastRVVRegisterAllocator() {
354 return createFastRegisterAllocator(onlyAllocateRVVReg, false);
355}
356
357static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",
358 "basic register allocator",
359 createBasicRVVRegisterAllocator);
360static RVVRegisterRegAlloc
361 greedyRegAllocRVVReg("greedy", "greedy register allocator",
362 createGreedyRVVRegisterAllocator);
363
364static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",
365 createFastRVVRegisterAllocator);
366
367class RISCVPassConfig : public TargetPassConfig {
368public:
369 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
370 : TargetPassConfig(TM, PM) {
371 if (TM.getOptLevel() != CodeGenOptLevel::None)
372 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
373 setEnableSinkAndFold(EnableSinkFold);
374 EnableLoopTermFold = true;
375 }
376
377 RISCVTargetMachine &getRISCVTargetMachine() const {
378 return getTM<RISCVTargetMachine>();
379 }
380
381 void addIRPasses() override;
382 bool addPreISel() override;
383 void addCodeGenPrepare() override;
384 bool addInstSelector() override;
385 bool addIRTranslator() override;
386 void addPreLegalizeMachineIR() override;
387 bool addLegalizeMachineIR() override;
388 void addPreRegBankSelect() override;
389 bool addRegBankSelect() override;
390 bool addGlobalInstructionSelect() override;
391 void addPreEmitPass() override;
392 void addPreEmitPass2() override;
393 void addPreSched2() override;
394 void addMachineSSAOptimization() override;
395 FunctionPass *createRVVRegAllocPass(bool Optimized);
396 bool addRegAssignAndRewriteFast() override;
397 bool addRegAssignAndRewriteOptimized() override;
398 void addPreRegAlloc() override;
399 void addPostRegAlloc() override;
400 void addFastRegAlloc() override;
401 bool addILPOpts() override;
402
403 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
404};
405} // namespace
406
408 return new RISCVPassConfig(*this, PM);
409}
410
411std::unique_ptr<CSEConfigBase> RISCVPassConfig::getCSEConfig() const {
412 return getStandardCSEConfigForOpt(TM->getOptLevel());
413}
414
415FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
416 // Initialize the global default.
417 llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,
418 initializeDefaultRVVRegisterAllocatorOnce);
419
420 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
421 if (Ctor != useDefaultRegisterAllocator)
422 return Ctor();
423
424 if (Optimized)
425 return createGreedyRVVRegisterAllocator();
426
427 return createFastRVVRegisterAllocator();
428}
429
430bool RISCVPassConfig::addRegAssignAndRewriteFast() {
431 addPass(createRVVRegAllocPass(false));
432 addPass(createRISCVInsertVSETVLIPass());
433 if (TM->getOptLevel() != CodeGenOptLevel::None &&
434 EnableRISCVDeadRegisterElimination)
435 addPass(createRISCVDeadRegisterDefinitionsPass());
436 return TargetPassConfig::addRegAssignAndRewriteFast();
437}
438
439bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
440 addPass(createRVVRegAllocPass(true));
441 addPass(createVirtRegRewriter(false));
442 addPass(createRISCVInsertVSETVLIPass());
443 if (TM->getOptLevel() != CodeGenOptLevel::None &&
444 EnableRISCVDeadRegisterElimination)
445 addPass(createRISCVDeadRegisterDefinitionsPass());
446 return TargetPassConfig::addRegAssignAndRewriteOptimized();
447}
448
449void RISCVPassConfig::addIRPasses() {
450 addPass(createAtomicExpandLegacyPass());
451 addPass(createRISCVZacasABIFixPass());
452
453 if (getOptLevel() != CodeGenOptLevel::None) {
454 if (EnableLoopDataPrefetch)
455 addPass(createLoopDataPrefetchPass());
456
457 addPass(createRISCVGatherScatterLoweringPass());
458 addPass(createInterleavedAccessPass());
459 addPass(createRISCVCodeGenPreparePass());
460 }
461
462 TargetPassConfig::addIRPasses();
463}
464
465bool RISCVPassConfig::addPreISel() {
466 if (TM->getOptLevel() != CodeGenOptLevel::None)
467 addPass(createRISCVPromoteConstantPass());
468 if (TM->getOptLevel() != CodeGenOptLevel::None) {
469 // Add a barrier before instruction selection so that we will not get
470 // deleted block address after enabling default outlining. See D99707 for
471 // more details.
472 addPass(createBarrierNoopPass());
473 }
474
475 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
476 EnableGlobalMerge == cl::BOU_UNSET) ||
477 EnableGlobalMerge == cl::BOU_TRUE) {
478 // FIXME: Like AArch64, we disable extern global merging by default due to
479 // concerns it might regress some workloads. Unlike AArch64, we don't
480 // currently support enabling the pass in an "OnlyOptimizeForSize" mode.
481 // Investigating and addressing both items are TODO.
482 addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
483 /* OnlyOptimizeForSize */ false,
484 /* MergeExternalByDefault */ true));
485 }
486
487 return false;
488}
489
490void RISCVPassConfig::addCodeGenPrepare() {
491 if (getOptLevel() != CodeGenOptLevel::None)
492 addPass(createTypePromotionLegacyPass());
493 TargetPassConfig::addCodeGenPrepare();
494}
495
496bool RISCVPassConfig::addInstSelector() {
497 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
498
499 return false;
500}
501
502bool RISCVPassConfig::addIRTranslator() {
503 addPass(new IRTranslator(getOptLevel()));
504 return false;
505}
506
507void RISCVPassConfig::addPreLegalizeMachineIR() {
508 if (getOptLevel() == CodeGenOptLevel::None) {
509 addPass(createRISCVO0PreLegalizerCombiner());
510 } else {
511 addPass(createRISCVPreLegalizerCombiner());
512 }
513}
514
515bool RISCVPassConfig::addLegalizeMachineIR() {
516 addPass(new Legalizer());
517 return false;
518}
519
520void RISCVPassConfig::addPreRegBankSelect() {
521 if (getOptLevel() != CodeGenOptLevel::None)
522 addPass(createRISCVPostLegalizerCombiner());
523}
524
525bool RISCVPassConfig::addRegBankSelect() {
526 addPass(new RegBankSelect());
527 return false;
528}
529
530bool RISCVPassConfig::addGlobalInstructionSelect() {
531 addPass(new InstructionSelect(getOptLevel()));
532 return false;
533}
534
535void RISCVPassConfig::addPreSched2() {
536 addPass(createRISCVPostRAExpandPseudoPass());
537
538 // Emit KCFI checks for indirect calls.
539 addPass(createKCFIPass());
540 if (TM->getOptLevel() != CodeGenOptLevel::None)
541 addPass(createRISCVLoadStoreOptPass());
542}
543
544void RISCVPassConfig::addPreEmitPass() {
545 // TODO: It would potentially be better to schedule copy propagation after
546 // expanding pseudos (in addPreEmitPass2). However, performing copy
547 // propagation after the machine outliner (which runs after addPreEmitPass)
548 // currently leads to incorrect code-gen, where copies to registers within
549 // outlined functions are removed erroneously.
550 if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
551 EnableRISCVCopyPropagation)
552 addPass(createMachineCopyPropagationPass(true));
553 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
554 addPass(createRISCVLateBranchOptPass());
555 // The IndirectBranchTrackingPass inserts lpad and could have changed the
556 // basic block alignment. It must be done before Branch Relaxation to
557 // prevent the adjusted offset exceeding the branch range.
558 addPass(createRISCVIndirectBranchTrackingPass());
559 addPass(&BranchRelaxationPassID);
560 addPass(createRISCVMakeCompressibleOptPass());
561}
562
563void RISCVPassConfig::addPreEmitPass2() {
564 if (TM->getOptLevel() != CodeGenOptLevel::None) {
565 addPass(createRISCVMoveMergePass());
566 // Schedule PushPop Optimization before expansion of Pseudo instruction,
567 // ensuring return instruction is detected correctly.
568 addPass(createRISCVPushPopOptimizationPass());
569 }
570 addPass(createRISCVExpandPseudoPass());
571
572 // Schedule the expansion of AMOs at the last possible moment, avoiding the
573 // possibility for other passes to break the requirements for forward
574 // progress in the LR/SC block.
575 addPass(createRISCVExpandAtomicPseudoPass());
576
577 // KCFI indirect call checks are lowered to a bundle.
578 addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
579 return MF.getFunction().getParent()->getModuleFlag("kcfi");
580 }));
581}
582
583void RISCVPassConfig::addMachineSSAOptimization() {
584 addPass(createRISCVVectorPeepholePass());
585 addPass(createRISCVFoldMemOffsetPass());
586
587 TargetPassConfig::addMachineSSAOptimization();
588
589 if (TM->getTargetTriple().isRISCV64()) {
590 addPass(createRISCVOptWInstrsPass());
591 }
592}
593
594void RISCVPassConfig::addPreRegAlloc() {
595 addPass(createRISCVPreRAExpandPseudoPass());
596 if (TM->getOptLevel() != CodeGenOptLevel::None) {
597 addPass(createRISCVMergeBaseOffsetOptPass());
598 addPass(createRISCVVLOptimizerPass());
599 }
600
601 addPass(createRISCVInsertReadWriteCSRPass());
602 addPass(createRISCVInsertWriteVXRMPass());
603 addPass(createRISCVLandingPadSetupPass());
604
605 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
606 addPass(&MachinePipelinerID);
607
608 addPass(createRISCVVMV0EliminationPass());
609}
610
611void RISCVPassConfig::addFastRegAlloc() {
612 addPass(&InitUndefID);
613 TargetPassConfig::addFastRegAlloc();
614}
615
616
617void RISCVPassConfig::addPostRegAlloc() {
618 if (TM->getOptLevel() != CodeGenOptLevel::None &&
619 EnableRedundantCopyElimination)
620 addPass(createRISCVRedundantCopyEliminationPass());
621}
622
623bool RISCVPassConfig::addILPOpts() {
624 if (EnableMachineCombiner)
625 addPass(&MachineCombinerID);
626
627 return true;
628}
629
631 PB.registerLateLoopOptimizationsEPCallback([=](LoopPassManager &LPM,
632 OptimizationLevel Level) {
633 if (Level != OptimizationLevel::O0)
635 });
636}
637
638yaml::MachineFunctionInfo *
642
643yaml::MachineFunctionInfo *
645 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
646 return new yaml::RISCVMachineFunctionInfo(*MFI);
647}
648
651 SMDiagnostic &Error, SMRange &SourceRange) const {
652 const auto &YamlMFI =
653 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
654 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
655 return false;
656}
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
static Reloc::Model getEffectiveRelocModel()
A
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
#define LLVM_ABI
Definition Compiler.h:213
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
DXIL Legalizer
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
F
#define F(x, y, z)
Definition MD5.cpp:55
I
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
T
#define T
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachinePipeliner("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden)
static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static cl::opt< bool > DisableVectorMaskMutation("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
This file defines a TargetTransformInfoImplBase conforming object specific to the RISC-V target machi...
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
const GCNTargetMachine & getTM(const GCNSubtarget *STI)
Y
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
X
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:69
LLVM_ABI std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition Attributes.cpp:474
LLVM_ABI unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition Attributes.cpp:468
LLVM_ABI StringRef getValueAsString() const
Return the attribute's value as a string.
Definition Attributes.cpp:400
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition Attributes.h:223
CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)
Lightweight error class with error context and mandatory checking.
Definition Error.h:159
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
Module * getParent()
Get the module that this global value is contained inside of...
Definition GlobalValue.h:663
This pass is responsible for selecting generic machine instructions to target-specific instructions.
A single uniqued string.
Definition Metadata.h:721
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Metadata * getModuleFlag(StringRef Key) const
Return the corresponding value if Key appears in module flags, otherwise return null.
Definition Module.cpp:353
static LLVM_ABI const OptimizationLevel O0
Disable as many optimizations as possible.
This class provides access to building LLVM's passes.
Definition PassBuilder.h:110
static LLVM_ABI PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition RegBankSelect.h:91
RegisterPassParser class - Handle the addition of new machine passes.
RegisterRegAllocBase class - Track the registration of register allocators.
Wrapper class representing virtual and physical registers.
Definition Register.h:20
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition SourceMgr.h:297
Represents a range in source code.
Definition SMLoc.h:47
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
std::string str() const
str - Get the contents as an std::string.
Definition StringRef.h:225
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
void setMachineOutliner(bool Enable)
Reloc::Model RM
void setCFIFixup(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
std::string TargetCPU
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:47
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Definition raw_ostream.h:692
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
@ Static
Definition CodeGen.h:25
@ BOU_UNSET
Definition CommandLine.h:639
initializer< Ty > init(const Ty &Val)
Definition CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVLandingPadSetupPass()
FunctionPass * createRISCVLoadStoreOptPass()
LLVM_ABI FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVFoldMemOffsetPass()
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
LLVM_ABI char & InitUndefID
Definition InitUndef.cpp:105
LLVM_ABI FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
LLVM_ABI FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createRISCVPostRAExpandPseudoPass()
LLVM_ABI Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false, bool MergeConstAggressiveByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVFoldMemOffsetPass(PassRegistry &)
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
FunctionPass * createRISCVVLOptimizerPass()
LLVM_ABI char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
void initializeRISCVLateBranchOptPass(PassRegistry &)
void initializeRISCVRedundantCopyEliminationPass(PassRegistry &)
Target & getTheRISCV64beTarget()
LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition CSEInfo.cpp:89
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
LLVM_ABI char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
auto dyn_cast_or_null(const Y &Val)
Definition Casting.h:753
FunctionPass * createRISCVPostLegalizerCombiner()
PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager
The Loop pass manager.
LLVM_ABI char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition MathExtras.h:279
ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
LLVM_ABI char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
LLVM_ABI FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition KCFI.cpp:61
void initializeRISCVVMV0EliminationPass(PassRegistry &)
void initializeRISCVInsertWriteVXRMPass(PassRegistry &)
void initializeRISCVLoadStoreOptPass(PassRegistry &)
LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
LLVM_ABI FunctionPass * createLoopDataPrefetchPass()
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:167
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
void initializeRISCVExpandAtomicPseudoPass(PassRegistry &)
FunctionPass * createRISCVPreLegalizerCombiner()
FunctionPass * createRISCVVMV0EliminationPass()
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
FunctionPass * createRISCVO0PreLegalizerCombiner()
CodeGenOptLevel
Code generation optimization level.
Definition CodeGen.h:82
@ Default
-O2, -Os
Definition CodeGen.h:85
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
Definition PassManager.h:668
FunctionPass * createRISCVIndirectBranchTrackingPass()
FunctionPass * createRISCVOptWInstrsPass()
LLVM_ABI FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
std::unique_ptr< ScheduleDAGMutation > createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)
LLVM_ABI FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
LLVM_ABI void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition GlobalISel.cpp:17
LLVM_ABI void initializeKCFIPass(PassRegistry &)
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
LLVM_ABI char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
LLVM_ABI ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeRISCVVLOptimizerPass(PassRegistry &)
LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeRISCVOptWInstrsPass(PassRegistry &)
LLVM_ABI FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
FunctionPass * createRISCVLateBranchOptPass()
Target & getTheRISCV64Target()
ModulePass * createRISCVPromoteConstantPass()
FunctionPass * createRISCVVectorPeepholePass()
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition Threading.h:86
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
void initializeRISCVIndirectBranchTrackingPass(PassRegistry &)
void initializeRISCVPromoteConstantPass(PassRegistry &)
void initializeRISCVAsmPrinterPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
LLVM_ABI FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition VirtRegMap.cpp:782
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
BumpPtrAllocatorImpl<> BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition Allocator.h:383
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition bit.h:330
FunctionPass * createRISCVInsertWriteVXRMPass()
LLVM_ABI MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVVectorPeepholePass(PassRegistry &)
FunctionPass * createRISCVZacasABIFixPass()
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
Target & getTheRISCV32beTarget()
void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:867
N
#define N
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)
Factory function: default behavior is to call new using the supplied allocator.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
MachineFunction & MF
Definition MIParser.h:167
static bool isRVVRegClass(const TargetRegisterClass *RC)
RegisterTargetMachine - Helper template for registering a target machine implementation,...
The llvm::once_flag structure.
Definition Threading.h:67
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
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