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	`1`	`+// Dynamic pattern detector implicit style fsm`
	`2`	`+module dyn_pattern_imp(clk, rst, valid, in, out, pattern);`
	`3`	`+`
	`4`	`+// N bit pattern detector`
	`5`	`+parameter BITS = 5;`
	`6`	`+`
	`7`	`+input clk, rst, valid, in;`
	`8`	`+input [BITS-1 : 0] pattern;`
	`9`	`+output reg out;`
	`10`	`+`
	`11`	`+reg [BITS-1 : 0] buffer;`
	`12`	`+integer count;`
	`13`	`+`
	`14`	`+always @ (posedge clk) begin`
	`15`	`+ if (rst == 1) begin`
	`16`	`+ buffer = 0;`
	`17`	`+ out = 0;`
	`18`	`+ count = 0;`
	`19`	`+ end`
	`20`	`+ else begin`
	`21`	`+ if (valid == 1) begin`
	`22`	`+ buffer = {buffer[BITS-2 : 0], in};`
	`23`	`+ count = count + 1;`
	`24`	`+ if (count == BITS) begin`
	`25`	`+ if (buffer == pattern) begin`
	`26`	`+ out = 1;`
	`27`	`+ // NON-OVERLAPPING `
	`28`	`+ count = 0;`
	`29`	`+ // OVERLAPPING `
	`30`	`+ //count = count -1;`
	`31`	`+ end`
	`32`	`+ else begin`
	`33`	`+ out = 0;`
	`34`	`+ count = count - 1;`
	`35`	`+ end`
	`36`	`+ end`
	`37`	`+ else out = 0;`
	`38`	`+ end`
	`39`	`+ else out = 0;`
	`40`	`+ end`
	`41`	`+end`
	`42`	`+`
	`43`	`+endmodule`

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	`1`	+`include "dynamic_pattern_imp.v"
	`2`	`+module tb;`
	`3`	`+`
	`4`	`+parameter BITS=8;`
	`5`	`+`
	`6`	`+reg clk, rst, valid, in;`
	`7`	`+reg [BITS-1 : 0] pattern;`
	`8`	`+wire out;`
	`9`	`+`
	`10`	`+`
	`11`	`+dyn_pattern_imp # (.BITS(BITS)) u0 (.clk(clk), .rst(rst), .valid(valid), .in(in), .out(out), .pattern(pattern));`
	`12`	`+`
	`13`	`+always #1 clk = ~clk;`
	`14`	`+`
	`15`	`+initial begin`
	`16`	`+ clk = 0;`
	`17`	`+ valid = 0;`
	`18`	`+ in = 0;`
	`19`	`+ pattern = 0;`
	`20`	`+`
	`21`	`+ rst = 1;`
	`22`	`+ repeat (5) @ (posedge clk);`
	`23`	`+ rst = 0;`
	`24`	`+`
	`25`	`+ pattern = $random;`
	`26`	`+ valid = 1;`
	`27`	`+ repeat (300) begin`
	`28`	`+ in = $random;`
	`29`	`+ @ (posedge clk);`
	`30`	`+ end`
	`31`	`+ valid = 0;`
	`32`	`+`
	`33`	`+ rst = 1;`
	`34`	`+ repeat (10) @ (posedge clk);`
	`35`	`+ rst = 0;`
	`36`	`+`
	`37`	`+ repeat (5) @ (posedge clk);`
	`38`	`+ $finish;`
	`39`	`+end`
	`40`	`+`
	`41`	`+endmodule`

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