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1 | 1 | # Dynamic pattern detector using verilog |
2 | 2 | A project to implement dynamic pattern detector using verilog in different ways. |
| 3 | +- Dynamic pattern detector with variable number of bits in implicit style fsm which supports APB protocol to configure pattern register value. |
| 4 | +- Dynamic 3 bit pattern detector in explicit style fsm. |
| 5 | +- Dynamic pattern detector with variable number of bits in implicit style fsm. |
| 6 | + |
| 7 | +--- |
| 8 | +**Files** |
| 9 | +1. Implicit fsm with APB [design](!!!) and [testbench](!!!) |
| 10 | +2. Explicit fsm [design](dynamic_pattern_exp.v) and [testbench](tb_dynamic_pattern_exp.v) |
| 11 | +3. Implicit fsm [design](dynamic_pattern_imp.v) and [testbench](tb_dynamic_pattern_imp.v) |
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