Shift, Zero, Overflow

Now to explain, how "shift right" works.

Imagine two 74573 transparent latches, wired together like that:

IC1 simply passes the ALU output through, when there is no "shift right".
For "shift right", the outputs of IC1 are turned off, and IC2 takes over.
Note, how the inputs of IC2 are connected.
I1 becomes Q0, I2 becomes Q1 and so on, so the Byte which is passed through IC2
is shifted right by one Bit. It's easy.

Another option would have been using 74257 multiplexers instead of 74573 latches,
but buying 74257 is more difficult than buying 74573.

(And when trying to build a pipelined CPU, you could replace the 74573 by 74574
edge triggered latches and hide the shifter "inside" the pipeline.)

The shifter in TREX is a bit more complicated than the previous example, imagine
a third 74573 which reads the external data bus, with outputs connected to Q0..7
from IC1 and IC2. You sure can imagine, that this would require three output enable
signals...

Also, the bus is 32 Bit wide, so passing the ALU output through, shifting it right
or reading a value from the external data bus takes 3 * 4 = 12 74573 in total.

For detecting that the 32 Bit shifter output is zero, we basically would need a
32 input NOR gate.

One approach would be to take four 7425 (each one containing two NOR gates
with four inputs), and to connect the outputs of the eight NOR gates to the inputs
of a 7430 NAND. But it's difficult to buy 7425 nowadays.
(Note, that you would have to invert the output of the 7430 before writing it
into the zero flag.)

Another approach would be resorting to the 7427, which contains three NOR gates,
each gate has three inputs.
But it might complicate the PCB layout, and an 8 input 7430 NAND wouldn't be
enough for testing the outputs of 11 NOR gates, so it's either improvising something
with one 7408, or replacing the 7430 with a 74133 13 input NAND gate.

Since we are using 74688 8 Bit comparators in another part of the CPU (and as
part of the address decoder on all the peripheral/memory PCBs to come), we did
decide for a different approach: using four 74688 to compare each Byte from the
shifter output against zero, and a 74151 multiplexer configurated to work as a
4 input NOR, so that the signal routed to the zero flag has the right polarity.

The overflow detection works exactly like in my article about the V_Flag:
a 74151 with select inputs connected to the uppermost Bit of the ALU data inputs
and output, fed by a "lookup table" generated from the ALU control signals.

A31, B31 and Q31 (or F31 in the schematic) are pins on the 74181 ALU IC
which processes the uppermost 4 Bits of the data.

Ok, so this schematic is a little bit simplified...

[HOME] [UP]/ [BACK] [1] [2] [3] [4] [5] [6] [7] [8] [NEXT]