The TREX architecture

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| The equations are spread over multiple GALs, |
| so debugging them is nearly as much fun |
| as playing "Minesweeper". |
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TREX is a TTL RISC experiment,

a 32 Bit CPU with a minimalistic instruction set.

This article describes, what some of the function blocks may
look like, how they are connected, and how a serious bug
went into our design.

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• Foreword
• Architectures
• Building Registers
• Shift, Zero, Overflow
• Status Register
• The bug stops here
• PC/LR swap, predecoder
• Conclusion

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(c) Dieter Mueller 2007, 2008