Use these tags to explore our category pages to learn more
Oct 23, 2025 / 5 min read
Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but this approach risks suboptimal performance and costly late-stage fixes. Advances in implementation tools and engineering change order (ECO) processes have improved scalability and convergence, yet challenges remain in achieving full timing visibility during optimization. The Adaptive Scenario Compression Technology offers a solution by compressing multiple scenarios into manageable sets while preserving critical timing information, enabling comprehensive optimization with reduced ECO cycles. Early adopters, including Samsung and Intel, have demonstrated significant improvements in timing violations and 50% reduction in ECO iterations, enhancing design quality and predictability.
Modern semiconductor chips are characterized by a complex array of timing scenarios, often exceeding hundreds. These scenarios arise from various operating modes, compounded by factors like process variations, temperature fluctuations, and voltage changes. Additionally, it can be further increased by the inclusion aging effects, electromigration, and other multi-physics phenomena that may impact chip performance over time.
Mobile and automotive designs exhibit the most diverse timing scenarios. Mobile chips must accommodate multiple operational modes, including low-power modes for extended standby, typical modes for responsiveness, and high-performance modes for gaming. Automotive chips prioritize reliability and safety, requiring performance under extreme conditions, such as high heat or freezing temperatures, while ensuring a long service life of 10 to 20 years.
Designers are responsible for optimizing semiconductor chips across a wide range of scenarios. This optimization process is complex; each additional scenario adds a new dimension to the design challenge, requiring consideration of performance metrics, power consumption, and design area, which can extend time-to-results and increase computational demands. Designers must balance thorough optimization with practical resource management to meet performance expectations while adhering to project timelines and budgets.
To streamline optimization, designers select a limited number of critical scenarios—typically around a dozen—based on past experiences and preliminary trials. This focus allows for a more efficient optimization process with a manageable computational footprint. Remaining scenarios are only addressed during design analysis and signoff stages. This two-tiered approach helps maintain a balance between thoroughness and efficiency.
Using only a subset of scenarios can skew optimization algorithms, prioritizing selected scenarios at the expense of others, leading to sub-optimal performance and power efficiency. Non-compliance issues, such as timing violations, may arise during the evaluation of excluded scenarios, resulting in extensive engineering change order (ECO) cycles that are time-consuming and resource-intensive. In modern designs, particularly in mobile and automotive sectors, the number of excluded scenarios can lead to numerous issues identified during signoff, often consuming over one-third of the design schedule on ECO iterations, extending timelines and increasing costs.
Modern solutions like Synopsys Fusion Compiler have improved the scalability of scenarios for design implementation, allowing for efficient optimization across 20-30 scenarios, a significant increase from the previous single-digit capacity. Additionally, advancements in ECO solutions like Synopsys PrimeClosure with increased physical awareness and integration of built-in physical engines, can minimize the back-and-forth interactions between implementation and signoff tools.
Despite these advancements, a challenge remains in expanding complete timing scenario visibility during optimization. Various methodologies have been proposed to analyze scenario criticality, but success has been limited due to high timing variability and differing criticality levels across optimization types. For instance, a scenario that may not be critical for setup time optimization could become essential during design rule check (DRC) optimization. This variability complicates decision-making and highlights the need for robust methodologies to ensure all relevant scenarios are considered throughout the design lifecycle.
The Adaptive Scenario Compression Technology effectively addresses the need for enhanced coverage while minimizing the impact on system capacity. This innovative approach intelligently compresses scenario databases (DBs) generated through the automated execution of Synopsys Golden Signoff Solutions, PrimeTime and StarRC, ensuring that implementation and optimization workflows can efficiently cover a wide array of scenarios, uniquely with Golden Signoff configuration and accuracy, without straining system resources.
A significant drawback of traditional scenario selection methodologies is the complete loss of visibility for non-critical scenarios that are filtered out. The Adaptive Scenario Compression Technology overcomes this challenge by creating models that retain essential timing characteristics from a large set of timing scenarios, compressing them into a reduced set of scenario views. This retention of critical information allows for better-informed decision-making during the design optimization process.
Furthermore, recognizing that scenario criticality and roles differ across various optimization objectives, the adaptive technique tailors its compression strategy and modeling to suit each specific optimization type. This flexibility enables comprehensive coverage that supports concurrent multi-objective physical optimization, ensuring that all relevant scenarios are considered in the design process.
The integration of comprehensive signoff scenario views into the design implementation workflow results in improved power, performance, and area (PPA) metrics, while also accelerating time-to-results (TTR). By applying full physical optimization techniques across all design scenarios, this methodology enhances overall design quality and reduces the downstream effort required for signoff engineering change orders (ECOs). By targeting a post-implementation total negative slack (TNS) reduction of over 95%, this approach significantly decreases the number of ECO iterations, thereby streamlining the design cycle and expediting time-to-market.
Samsung, a world-leading Mobile SoC provider and an early development partner of this technology, shared their insights during the 2025 Synopsys User Group (SNUG) event in India. By deploying adaptive scenario compression technology to facilitate block level closure in Fusion Compiler across eight unique designs, the team achieved remarkable results: an average reduction of 77.28% in setup violations, 91.5% in hold violations, and 89.65% in maximum transition time violations post-implementation, as evaluated across all signoff scenarios.
The significant improvements across these metrics were attributed to the effective compression of over 50 scenarios into the implementation flow, all while maintaining minimal runtime overhead. This advancement led to an impressive average reduction of 53.4% in engineering change order (ECO) cycles compared to traditional methods.
These outcomes highlight the efficacy of the adaptive scenario compression technology in enhancing design performance and efficiency. For further details on this case study and additional findings, please refer to the SNUG proceedings. "Fast tracking ECO cycles using Block Level Closure" Authored by Deep Kalola, Utkarsh Agarwal, and Preetham V. from Samsung.
Intel, a world-leading provider of high-performance computing (HPC) SoC solutions and an early development partner of this technology, shared valuable insights at the 2025 Synopsys User Group (SNUG) event in India. The adaptive scenario compression technology expanded timing scenario views within Fusion Compiler and ensured alignment of static timing analysis (STA) settings and constraints between the implementation and signoff phases. In three distinct high-utilization test cases, including one with 80% utilization that previously necessitated multiple engineering change order (ECO) iterations for closure, the accurate and comprehensive timing view provided by Fusion Compiler enabled accelerated timing closure, requiring only a single ECO iteration.
For further details on this case study and additional findings, please refer to the SNUG proceedings. "Accelerating Time to Market by Left-Shifting Signoff Convergence" Authored by Anju KC, Rajiv Girdhar, and Manjunath GC from Intel
Another leading Automotive SoC provider and early development partner successfully evaluated the technology on an advanced ADAS design utilizing a 3nm technology process, which comprises over 8 million instances. The adaptive scenario compression technology achieved a remarkable 95% reduction in hold total negative slack (TNS), a critical metric that often contributes to increased engineering change order (ECO) iterations. This improvement resulted in a 50% reduction in ECO iterations, significantly enhancing the predictability of achieving signoff closure.