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1 vote
0 answers
77 views

I'm currently learning about compiler backends and came across a question while studying some ARMv7 assembly generated by GCC. I'm not entirely sure about this, but I'd appreciate any insights. Given ...
3 votes
1 answer
172 views

When assembling the following with NASM: BITS 64 push 32767 I get 68 ff 7f 00 00. This is interesting to me, since this is the 32b encoding (push dword). Any ideas why it doesn't resort to the 16b ...
1 vote
0 answers
118 views

This is a weird one. I'm using gcc to assemble a program and I want to know if the value in register rsi fits in 32 bits, so I use this instruction: cmpq 0ドルxffffffff, %rsi I get back an error that ...
2 votes
0 answers
164 views

I'm currently learning ARM64 assembly and I'm having trouble understanding how bitmask immediates are implemented and validated. I've read that ARM64 has specific rules for what constitutes a valid ...
2 votes
1 answer
206 views

After a long time I have to use the GNU assembler again. Ever since I had trouble with the '$'. The manual just says: 3.6.2.1 Integers A decimal integer starts with a non-zero digit followed by zero ...
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0 votes
1 answer
333 views

I am trying to write a program in ARMv8 AArch64 (ARM64 if you prefer) and I want to move a very large number into a 32-bit register. From what I know, the correct format is mov w20, 36383899 However, ...
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0 votes
1 answer
116 views

I'm working on parsing RISC-V assembly, and am working on parsing immediates. Using the LUI instruction as an example, I'm seeing examples which write it like lui t0, 0, and examples which write it ...
0 votes
1 answer
2k views

I have the following binary from a RISC-V instruction that I need to decode: 11111110000011100001100011100011 Using the RISC-V reference card, I know the following information: Its opcode is 1100011, ...
2 votes
1 answer
375 views

Is there a constraint for x86-64 that is similar to the "i" constraint, but that only matches when the operand value fits in a 32-bit signed immediate? For the function shown below, I would ...
0 votes
0 answers
121 views

I am having trouble performing logical instructions on the ARMv8-a architecture. for example, "and x13, x13, #0x0000CCCC0000CCCC" or "and x13, x13, #0x0A0A0A0A0A0A0A0A" results in ...
0 votes
1 answer
78 views

When I have the following code: int value2 = 0x11223344; The VS2022 compiler (arm64) generates: StarFunction PROC ... ldr w8,|value_label| ... ... ... ret |value_label| DCD ...
1 vote
0 answers
454 views

GNU ARM assembler supports prefixes to extract group of bytes from a relocation value https://sourceware.org/binutils/docs/as.html#ARM_002dRelocations On ARMv7m and later, the low/high 16 bit ...
3 votes
1 answer
634 views

ARM64 instructions are 32-bit long, so normally a data section is used to store literals if one wants to use a 64-bit floating point constant number. However, I found in some cases where AArch64 gcc ...
0 votes
0 answers
325 views

there is a difference between those two instructions? addI 12,ドル1,0ドルx0000ffff vs addI 12,ドル1,0ドルxffff I need to know what is the value of 12ドル after those instruction : lui 1,0ドルxffffff00 addi 12,ドル1,ドル...
4 votes
1 answer
878 views

In NASM (2.14.02), the instruction add rbx, 0xffffffff leads to warning: signed dword value exceeds bounds [-w+number-overflow] I'm aware that arithmetic-logic operations in 64-bit mode only accept ...

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