According to the documentation, the SAADC (ADC) device has a maximum sampling rate of 200kHz (ksps), a value that is the sum of a minimum TACQ (acquisition time) of 3us and a conversion time of "<2us".
In our application, we use a TACQ of 10 or 5us, a 12-bit sample, sometimes 4x oversampling and use EasyDMA to send the data to a RAM buffer. We do a sampling series consisting of one voltage sample and one current sample eight times so sixteen samples in all. The characteristics of the inputs requires the SAADC be configured before a sample can be issued.
Our results show that the voltage requires 19.5us to complete and current 33us. The former is made up of a 10us TACQ and a"<2us" conversion meaning there are 7.5us "unaccounted for". The latter is made up of a 5us TACQ, "<2u" conversion and with the 7.5us from the voltage sampling it leaves 18.5us unaccounted for that probably have to do with the oversampling. I am assuming that the 7.5us is caused by reconfiguration and EasyDMA overhead.
The nRF52840 ARM core runs at 64MHz which means that configuration and interrupt code overhead should not "cost" more than 2-3us.
We have tried using different sampling lengths (8- or 12-bit results) but this does not affect the overall time or, it seems, the "<2us" conversion time.
So my question is: do these results appear reasonable given that our setup is somewhat complicated or is there some silver bullet feature that we have overlooked - in particular for the current sampling?