Summary

wolfBoot runs standalone in M-mode on the E51 monitor core, replacing both HSS and OpenSBI: it brings up LPDDR4 in software, secure-boots a signed Yocto FIT from SD, and stays resident as a minimal SBI runtime so the U54 cores boot Linux. Result: secure-boot 4-CPU SMP Yocto Linux to a login prompt in ~40 s from power-on, with no Microchip firmware in the boot chain.

Commits

1. PolarFire SoC: LPDDR4 DDR init for MPFS250T Video Kit (M-Mode) - software LPDDR4 init/training (all-4-lane WRCALIB gate + retry), SD secure boot of a signed Yocto FIT (SDHCI PIO + PDMA-to-DDR staging with read-back verify), SHA384 + ECC384 verification, FIT parse, L2 dtb fixups, and S-mode hand-off. The licensed Cadence DDR controller logic (controller CSR programming, Memory Test Controller, LPDDR4 mode-register protocol) is a target-independent driver in src/ddr_cadence.c + include/ddr_cadence.h; the Microchip PHY/PLL/clock/training and the board LIBERO_SETTING_* values stay in hal/mpfs250_ddr.c.
2. RISC-V: minimal SBI runtime; PolarFire SoC boots 4-CPU SMP Yocto Linux - a minimal M-mode SBI runtime (src/riscv_sbi.c): BASE/TIME/IPI/RFENCE/HSM/DBCN plus the legacy calls, with per-hart M-mode trap stacks, rdtime and misaligned load/store emulation, atomic cross-hart IPI ops with self-directed SSIP delivery, and the trap-entry / M->S hand-off wiring. PolarFire SoC bring-up adds CLINT MTIME enable, per-hart HSM hart_start mailboxes, the watchdog policy, and the dtb fixups that bring up 4-CPU SMP Linux.

Key design points

• Generic Cadence driver: the controller half is reusable across Cadence-DDR SoCs (controller base overridable via DDR_CADENCE_CTRL_BASE); the SoC-specific PHY/PLL/training is behind the platform HAL. Both compile only when MPFS_DDR_INIT is set.
• Cross-hart state in DTIM, not L2-scratch: cacheable stores to the L2 scratchpad can be lost on dirty-line eviction, so the SBI shared state, HSM mailboxes and the secondary-hart release gate live in the E51 DTIM; the M-mode trap stacks live in reserved DDR.
• No timer/rdtime CSR on these harts: CLINT MTIME is enabled from SYSREG and rdtime is emulated in M-mode for S and U mode.
• Watchdog policy: the MSS watchdogs always count and reset the chip and cannot be disabled, so the parked E51 monitor refreshes all five and the OS watchdog nodes are disabled in the dtb.
• DDR data path: direct CPU writes to DDR do not land on this board, so the kernel/dtb copies and the SD load go through the PDMA master with a non-cached read-back verify.

Validation (MPFS250T Video Kit, power-controlled cold boots)

• 5/5 and repeated 3/3 clean cold boots to the systemd login prompt; smp: Brought up 1 node, 4 CPUs with zero "failed to come online"; login at ~40 s.
• 12-minute idle soaks with no watchdog reset.
• All five PolarFire template configs build (M-mode SD, M-mode QSPI, S-mode SDCard, S-mode QSPI, S-mode L2-LIM); the M-mode QSPI build links no ddr_cadence.o (driver correctly gated). versal_vmk180_sdcard, zynqmp_sdcard, zynq7000_sdcard also build (shared sdhci/boot files).
• The S-mode SDCard, S-mode QSPI, S-mode L2-LIM and M-mode QSPI configs were each booted on hardware via HSS to confirm no regression.

Notes for reviewers

• src/vector_riscv.S trap-macro changes are WOLFBOOT_RISCV_MMODE-gated; S-mode builds keep the original frame behavior.
• src/sdhci.c keeps the cross-platform driver clean: the MPFS PDMA/watchdog specifics are behind weak sdhci_platform_block_copy() / sdhci_platform_wdt_pet() hooks.
• src/fdt.c gains a weak wolfBoot_fit_memcpy hook so the platform can route FIT subimage copies through PDMA.
• CI: tools/ci/mpfs_libero_stub/fpga_design_config.h lets the M-mode + DDR path compile in GitHub Actions (compile-only; not runnable).
• lib/wolfssl submodule pointer is bumped (came in with the DDR work); drop it if the project prefers to bump separately.
• docs/Targets.md documents the M-mode + DDR Linux boot flow, the wolfSBI runtime, the watchdog policy, and the generic Cadence driver split.