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RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

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whutddk/RiftCore

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RiftCore

License

RiftCore is a 9-stage, single-issue, out of order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache system.

The further versions will be moved to Rift2Core. Chisel3 will be used to develop.

architecture

Status

Last Commit GitHub last commit Status GitHub Workflow Status Support ISA ISA
ISA
rv64ui-p-add rv64ui-p-addiw rv64ui-p-addw rv64ui-p-and rv64ui-p-andi rv64ui-p-auipc
rv64ui-p-beq rv64ui-p-bge rv64ui-p-bgeu rv64ui-p-blt rv64ui-p-bltu rv64ui-p-bne
rv64ui-p-jal rv64ui-p-jalr rv64ui-p-lb rv64ui-p-lbu rv64ui-p-ld rv64ui-p-lh
rv64ui-p-lhu rv64ui-p-lui rv64ui-p-lw rv64ui-p-lwu rv64ui-p-or rv64ui-p-ori
rv64ui-p-sb rv64ui-p-sd rv64ui-p-sh rv64ui-p-sll rv64ui-p-slli rv64ui-p-slliw
rv64ui-p-sllw rv64ui-p-slt rv64ui-p-slti rv64ui-p-sltiu rv64ui-p-sltu rv64ui-p-sra
rv64ui-p-srai rv64ui-p-sraiw rv64ui-p-sraw rv64ui-p-srl rv64ui-p-srli rv64ui-p-srliw
rv64ui-p-srlw rv64ui-p-sub rv64ui-p-subw rv64ui-p-sw rv64ui-p-xor rv64ui-p-xori
rv64mi-p-access rv64mi-p-breakpoint rv64mi-p-csr rv64mi-p-ma_addr rv64mi-p-ma_fetch rv64mi-p-mcsr
rv64ui-p-fence_i rv64ui-p-simple rv64mi-p-illegal
ISA
rv64uc-p-rvc
ISA
rv64um-p-mul rv64um-p-mulh rv64um-p-mulhsu rv64um-p-mulhu rv64um-p-mulw rv64um-p-div
rv64um-p-divu rv64um-p-divuw rv64um-p-divw rv64um-p-rem rv64um-p-remu rv64um-p-remuw
rv64um-p-remw

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dhrystone

dhrystone of each commit

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RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

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