This repository contains projects created for the Zoom Marathon Challenge. Each project focuses on different topics, including object equality, streams, serialization, and multithreading. Explore the code, videos, and documentation to enhance your understanding. Happy learning! π₯π
In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.
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