Opensource DDR3 Controller
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Dec 29, 2025 - Verilog
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phy
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An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
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Sep 14, 2023 - Verilog
Open Sigfox Stack Reference Implementation - Physical Layer for SDR
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Jun 12, 2020 - Python
Go package for parsing Source Engine StudioModel formats (.mdl, .vtx, .vvd, .phy)
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Nov 2, 2025 - Go
Plugins to Phy1 - additional features to Phy
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Nov 23, 2019 - Python
External PHY RTL8201F with switch RTL8305NB and 2xHR871181A
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Mar 3, 2024
Python module for 5G NR sync signals and decoding.
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Apr 13, 2022 - Python
External PHY RTL8201F with HR871181A
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Mar 3, 2024
Neural Signal Analysis
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Feb 21, 2025 - MATLAB
Plugins for the manual spike sorting program phy
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Sep 20, 2021 - Python
an 100% python navigator
python navigator tkinter nav phy tkinter-gui tkinter-python navigators pythonnavigator phynav 4lxprime
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Oct 23, 2022 - Python
Analysis of physical layer security of MIMO system using Machine Learning algorithms vs theoretical best
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Oct 28, 2021 - Jupyter Notebook
BRAVE is a collaborative research project started in January 2018, that aims at creating new physical-layer (PHY) techniques devoted to beyond-5G wireless communications. The partners (Siradel, Central-Supélec, CEA-Leti and ANFR) are designing new high-data-rate and energy-efficient waveforms that operate in frequencies above 90 GHz. Application...
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Jun 21, 2023
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