Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

• Updated Nov 25, 2025
• Verilog

Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry

• Updated Feb 25, 2021

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

• Updated Apr 26, 2023
• Verilog

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

• Updated Sep 28, 2025
• Verilog

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.

• Updated Jul 30, 2025

A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.

• Updated Sep 7, 2025
• Python