arithematic-circuits

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VLSI-Shubh / Delay-and-Power-Analysis-of-a-Static-8x8-Dadda-Multiplier-Circuit

High-speed ×ばつ8 Dadda multiplier designed in 45nm CMOS technology with hybrid transmission gate/CMOS logic. Features 4:2 compressor-based partial product reduction, critical path delay of 0.204ns, and comprehensive delay & power analysis.

vlsi-physical-design dadda-multiplier delay-analysis cmos-logic arithematic-circuits

Updated Mar 10, 2025

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arithematic-circuits

Here is 1 public repository matching this topic...

VLSI-Shubh / Delay-and-Power-Analysis-of-a-Static-8x8-Dadda-Multiplier-Circuit

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