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1. AgriGEE.lite AgriGEE.lite Public

   Because using satellite data shouldn't be rocket science, neither in code nor in hardware.

   Python 7 1

2. ee-s1-ard ee-s1-ard Public

   Forked from adugnag/gee_s1_ard

   This implementation enhances the Sentinel-1 SAR Backscatter ARD Preparation framework by making it a PyPI package.

   Python 14

3. simplified-mips-pipeline simplified-mips-pipeline Public

   A synthesizable simplified MIPS written in System Verilog

   SystemVerilog 3

4. cpp-boilerplate cpp-boilerplate Public

   My boilerplate for C++ 11 big projects. Based on vaalentin/cpp-boilerplate <3

   C++

5. presto presto Public

   PRESTO is a simulator for scheduling processes and physical memory made in Python 3, with a design highly inspired by htop.

   Python

6. lesc-ufv/cgra-routing lesc-ufv/cgra-routing Public

   SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.

   Verilog 11 2