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学习AXI接口,以及xilinx DDR3 IP使用
Verilog 40 15
download from opencores.org
Verilog 16 9
study uvm step by step
SystemVerilog 11 5
auto generate verilog testbench file
Lua 9 2
try write sata controller
Verilog 6 3
vivado non-project example
Tcl 4 4
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